Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 849-855

  Chakraborty, Ashutosh ^a   Shi, Sean X ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREAS; BENCHMARK DESIGNS; CYCLE TIME; CYCLE TIME REDUCTION; DESIGN CLOSURE; DEVICE MODELLING; MOORE'S LAWS; MOSFETS; OPTIMIZATION ITERATIONS; PERFORMANCE IMPROVEMENTS; PROCESS CHARACTERIZATION; RESEARCH WORKS; SILICON DEVICES; STANDARD-CELL LIBRARIES; STRAINED SILICON; STRAINED SILICON DEVICES; SUB-100 NM TECHNOLOGIES; TIMING OPTIMIZATION;

BENCHMARKING; ELECTRIC BATTERIES; INDUSTRIAL ENGINEERING; NONMETALS; OPTIMIZATION; SILICON; STANDARDS; TESTING; TIME MEASUREMENT;

MOSFET DEVICES;

EID: 49749144088     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484780     Document Type: Conference Paper

References (8)

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