Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip

Transactions on Embedded Computing Systems

Volumn 9, Issue 3, 2010, Pages

  Guang, Liang ^a   Nigussie, Ethiopia ^a   Rantala, Pekka ^a   Isoaho, Jouni ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

Design approach; Hierarchical monitoring; Parallel computing; System on chip

Indexed keywords

AGENT FRAMEWORK; AGENT MONITORING; APPLICATION REQUIREMENTS; DESIGN APPROACH; DESIGN APPROACHES; DESIGN PROCESS; MONITORING SERVICES; NETWORK ON CHIP; NEW DESIGN; PARALLEL COMPUTING SYSTEM; PARALLEL SYSTEM;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; MICROPROCESSOR CHIPS; MONITORING; PARALLEL ARCHITECTURES; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

HIERARCHICAL SYSTEMS;

EID: 77949449290     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1698772.1698783     Document Type: Article

References (46)

1. ASANOVIC, K., BODIK, R., CATANZARO, B. C., GEBIS, J. J., HUSBANDS, P., KEUTZER, K., PATTERSON, D. A., PLISHKER, W. L., SHALF, J., WILLIAMS, S. W., AND YELICK, K. A. 2006. The landscape of parallel computing research: A view from Berkeley. Tech. rep., University of California, Berkeley.
2. BELL, S., EDWARDS, B., AMANN, J., CONLIN, R., JOYCE, K., LEUNG, V.,MACKAY, J., REIF, M., BAO, L., BROWN, J., MATTINA, M., MIAO, C.-C., RAMEY, C., WENTZLAFF, D., ANDERSON, W., BERGER, E., FAIRBANKS, N., KHAN, D.,MONTENEGRO, F., STICKNEY, J., AND ZOOK, J. 2008. Tile64 - processor: A 64-core soc with mesh interconnect. In Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC'08). IEEE, 88-598.
3. BERNSTEIN, K., FRANK,D. J.,GATTIKER, A. E.,HAENSCH,W., JI, B. L.,NASSIF, S. R.,NOWAK, E. J., PEARSON, D. J., AND ROHRER, N. J. 2006. High-performance cmos variability in the 65-nm regime and beyond. IBM J. Resear. Devel. 50, 4/5, 433-449.
4. DICKINSON, D., MOSOVSKY, J., AND HOUTHUYSEN, S. 2003. Assessing integrated circuit manufacturing for environmental performance and sustainability: a full scale ic business application. In Proceedings of the IEEE International Symposium on Electronics and the Environment. IEEE Computer Society, Los Alamitos, CA, 214-219.
5. GUANG, L. AND JANTSCH, A. 2006. Adaptive power management for the on-chip communication network. In Proceedings of the 9th EUROMICRO DSD Conference. IEEE Computer Society, Los Alamitos, CA, 649-656.
6. GUANG, L., NIGUSSIE, E., KOSKINEN, L., AND TENHUNEN,H. 2009. Autonomous dvfs on supply islands for energy-constrained noc communication. In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS'09). Springer-Verlag, 183-194.
7. GUANG, L., RANTALA, P., NIGUSSIE, E., ISOAHO, J., AND TENHUNEN, H. 2008. Low-latency and energyefficient monitoring interconnect for hierarchical-agent- monitored nocs. In Proceedings of the NORCHIP. 227-232.
8. GUNTER, D., TIERNEY, B., JACKSON, K., LEE, J., AND STOUFER, M. 2002. Dynamic monitoring of highperformance distributed applications. In Proceedings of the 11th IEEE International Symposium on High Performance Distributed Computing HPDC-11. IEEE Computer Society, Los Alamitos, CA, 163-170.
9. HAENSCH, W., NOWAK, E. J., DENNARD, R. H., SOLOMON, P. M., BRYANT, A., DOKUMACI, O. H., KUMAR, A., WANG, X., JOHNSON, J. B., AND FISCHETTI, M. V. 2006. Silicon cmos devices beyond scaling. IBM J. Resear. Devel. 50, 4/5, 339-361.
10. HAZUCHA, P., SCHROM, G., HAHN, J., BLOECHEL, B., HACK, P., DERMER, G., NARENDRA, S., GARDNER, D., KARNIK, T., DE, V., AND BORKAR, S. 2005. A 233-mhz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid-State Circ. 40, 4, 838-845.
11. HE, S. AND TORKELSON,M. 1996. Anew approach to pipeline fft processor. In Proceedings of the 10th International Parallel Processing Symposium (IPPS'96). IEEE Computer Society, Los Alamitos, CA, 766-770.
12. HU, J. AND MARCULESCU, R. 2005. Energy and performance-aware mapping for regular noc architectures. IEEE Trans. CAD 24, 4, 551-562.
13. ITRS TECHNOLOGYWORKINGGROUP. 2007. International technology roadmap for semiconductors- design, 2007 Ed. ITRS Technology Working Group.
14. JANTSCH, A. 2003. Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation. Morgan Kaufmann Publishers Inc., San Francisco, CA.
15. JESSHOPE, C., MILLER, P., AND YANTCHEV, J. 1989. High performance communications in processor networks. In Proceedings of the 16th Annual International Symposium on Computer Architecture. ACM, New York, NY, 150-157.
16. KEUTZER, K., NEWTON, A., RABAEY, J., AND SANGIOVANNI-VINCENTELLI, A. 2000. System-level design: orthogonalization of concerns and platform-based design. IEEE Trans. CAD 19, 12, 1523-1543.
17. KIM,W., GUPTA, M.,WEI, G.-Y., AND BROOKS, D. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedingss of the IEEE 14th International Symposium on High Performance Computer Architecture (HPCA'08). 123-134.
18. KISSLER, D., STRAWETZ, A., HANNIG, F., AND TEICH, J. 2009. Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures. In Revised Selected Papers from PATMOS 2008. Springer-Verlag, 307-317.
19. KUMAR, S., JANTSCH, A., SOININEN, J., FORSELL, M.,MILLBERG, M., BERG, J., TIENSYRJ, K., AND HEMANI, A. 2002. A network on chip architecture and design methodology. In Proceedingss of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02). IEEE Computer Society, Los Alamitos, CA, 117.
20. LACKEY,D., ZUCHOWSKI, P.,BEDNAR, T., STOUT,D.,GOULD, S., ANDCOHN, J. 2002. Managing power and performance for system-on-chip designs using voltage islands. In Proceedingss of the IEEE/ACM International Conference on Computer Aided Design (ICCAD'02). ACM, New York, NY, 195-202.
21. LEHTONEN, T., LILJEBERG, P., AND PLOSILA, J. 2007. Online reconfigurable self-timed links for fault tolerant noc. VLSI Des. 13.
22. LIN, H.-L., LIN, H., CHEN, Y.-C., AND CHANG, R. 2004. A novel pipelined fast fourier transform architecture for double rate ofdm systems. In Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS'04). IEEE, 7-11.
23. MARCULESCU, R. 2004. Energy, fault-tolerance, and scalability issues in designing network-onchip. Tutorial at ASP-DAC.
24. OGRAS, U., MARCULESCU, R., CHOUDHARY, P., AND MARCULESCU, D. 2007. Voltage-frequency island partitioning for gals-based networks-on-chip. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC'07). ACM, New York, NY, 110-115.
25. RABAEY, J.M. 2007. Scaling the power wall: Revisiting the low-power design rules. In Proceedings of the International Symposium on System-on-chip (SoC'07).
26. RANTALA, P., ISOAHO, J., AND TENHUNEN, H. 2007. Agent-based reconfigurability for fault-tolerance in network-on-chip. In Proceedings of the Engineering of Reconfigurable Systems and Algorithms Conference (ERSA). CSREA Press, 207-210.
27. ROTA, S. R. AND ALMEIDA JR., J. R. D. 2004. Run-time monitoring for dependable systems: An approach and a case study. In Proceedings of the 23rd IEEE International Symposium on Reliable Distributed Systems (SRDS'04). IEEE Computer Society, Los Alamitos, CA, 41-49.
28. SANGIOVANNI-VINCENTELLI, A. 2002. Defining platform-based design. EEDesign of EETimes.
29. SANGIOVANNI-VINCENTELLI, A. AND MARTIN, G. 2001. Platform-based design and software design methodology for embedded systems. IEEE Des. Test of Comput. 18, 6, 23-33.
30. SCHATTKOWSKY, T. ANDMULLER,W. 2004. Model-based design of embedded systems. In Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing. IEEE, 113-128.
31. SHAMSHIRI, S., LISHERNESS, P., PAN, S.-J., AND CHENG, K.-T. 2008. A cost analysis framework for multi-core systems with spares. In Proceedings of the IEEE International Test Conference (ITC'08). 1-8.
32. SHANG, L., PEH, L.-S., AND JHA,N. 2003. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proceedings of the International Symposium of High Performance Computer Architecture (HPCA'03). IEEE Computer Society, Los Alamitos, CA, 91-102.
33. SOTERIOU, V. AND PEH, L.-S. 2007. Exploring the design space of self-regulating power-aware on/off interconnection networks. IEEE Trans. Parall. Distrib. Syst. 18, 3, 393-408.
34. STRATAKOS, A. J. 1998. High-efficiency low-voltage DC-DC conversion for portable applications. Ph.D. thesis, University of California, Berkeley.
35. SYLVESTER, D., BLAAUW, D., AND KARL, E. 2006. Elastic: An adaptive self-healing architecture for unpredictable silicon. IEEE Des. Test Comput. 23, 6, 484-490.
36. TAYLOR, M., KIM, J., MILLER, J., WENTZLAFF, D., GHODRAT, F., GREENWALD, B., HOFFMAN, H., JOHNSON, P., LEE, J.-W., LEE, W., MA, A., SARAF, A., SENESKI, M., SHNIDMAN, N., STRUMPEN, V., FRANK, M., AMARASINGHE, S., AND AGARWAL, A. 2002. The raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22, 2, 25-35.
37. TIERNO, J., RYLYAKOV, A., AND FRIEDMAN, D. 2008. A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 NM SOI. IEEE J. Solid-State Circ. 43, 1, 42-51.
38. TRUONG,D.,CHENG,W.,MOHSENIN, T.,YU, Z., JACOBSON, A., LANDGE,G.,MEEUWSEN, M.,WATNIK,C., TRAN, A., XIAO, Z., WORK, E., WEBB, J., MEJIA, P., AND BAAS, B. 2009. A 167-processor computational platform in 65 nm CMOS. IEEE J. Solid-State Circ. 44, 4, 1130-1144.
39. VANGAL, S., HOWARD, J., RUHL, G., DIGHE, S., WILSON, H., TSCHANZ, J., FINAN, D., IYER, P., SINGH, A., JACOB, T., JAIN, S., VENKATARAMAN, S., HOSKOTE, Y., AND BORKAR, N. 2007. An 80-tile 1.28tflops network-on-chip in 65nm CMOS. In Digest of Technical Papers. IEEE International Solid-State Circuits Conference (ISSCC'07). IEEE, International, 98-589.
40. VANGAL, S., HOWARD, J., RUHL, G., DIGHE, S., WILSON, H., TSCHANZ, J., FINAN, D., SINGH, A., JACOB, T., JAIN, S., ERRAGUNTLA, V., ROBERTS, C., HOSKOTE, Y., BORKAR, N., AND BORKAR, S. 2008. An 80-tile sub-100-w teraflops processor in 65-nm CMOS. IEEE J. Solid-State-Circ. 43, 1, 29-41.
41. WANG, H.-S., ZHU, X., PEH, L.-S., AND MALIK, S. 2002a. Orion: a power-performance simulator for interconnection networks. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society Press, Los Alamitos, CA, 294-305.
42. WANG, M., MADHYASTHA, T., CHAN, N. H., PAPADIMITRIOU, S., AND FALOUTSOS, C. 2002b. Data mining meets performance evaluation: fast algorithms for modeling bursty traffic. In Proceedings of the 18th International Conference on Data Engineering. IEEE Computer Society, Los Alamitos, CA, 507-516.
43. WHISNANT, K., KALBARCZYK, Z. T., AND IYER, R. K. 2003. A system model for dynamically reconfigurable software. IBM Syst. J. 42, 1, 45-59.
44. WIBBEN, J. AND HARJANI, R. 2007. A high efficiency dc-dc converter using 2nh on-chip inductors. In Proceedings of the IEEE Symposium on VLSI Circuits. 22-23.
45. ZERGAINOH, N.-E., BAGHDADI, A., AND JERRAYA, A. A. 2005. Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. J. Embedd. Syst. 1, 1/2, 112-124.
46. ZIPF, P. 2008. Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays. IEEE Trans. VLSI Syst. 16, 2, 134-143.