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Volumn 5349 LNCS, Issue , 2009, Pages 307-317

Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; DYNAMIC MODELS; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; INTEGRATED CIRCUITS; SYSTEMS ANALYSIS; TIME MEASUREMENT; TIMING CIRCUITS;

EID: 61649110992     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-95948-9_31     Document Type: Conference Paper
Times cited : (5)

References (16)
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    • Bouwens, F., Berekovic, M., Kanstein, A., Gaydadjiev, G.: Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, 4419, pp. 1-13. Springer, Heidelberg (2007)
    • Bouwens, F., Berekovic, M., Kanstein, A., Gaydadjiev, G.: Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, vol. 4419, pp. 1-13. Springer, Heidelberg (2007)
  • 5
    • 0031639693 scopus 로고    scopus 로고
    • Patel, R., Rajgopal, S., Singh, D., Baez, F., Mehta, G., Tiwari, V.: Reducing Power in High-Performance Microprocessors. DAC 00, 732-737 (1998)
    • Patel, R., Rajgopal, S., Singh, D., Baez, F., Mehta, G., Tiwari, V.: Reducing Power in High-Performance Microprocessors. DAC 00, 732-737 (1998)
  • 9
    • 37249015485 scopus 로고    scopus 로고
    • Kupriyanov, A., Hannig, F., Kissler, D., Teich, J., Lallet, J., Sentieys, O., Pillement, S.: Modeling of interconnection networks in massively parallel processor architectures. In: Lukowicz, P., Thiele, L., Tröster, G. (eds.) ARCS 2007. LNCS, 4415, pp. 268-282. Springer, Heidelberg (2007)
    • Kupriyanov, A., Hannig, F., Kissler, D., Teich, J., Lallet, J., Sentieys, O., Pillement, S.: Modeling of interconnection networks in massively parallel processor architectures. In: Lukowicz, P., Thiele, L., Tröster, G. (eds.) ARCS 2007. LNCS, vol. 4415, pp. 268-282. Springer, Heidelberg (2007)
  • 10
    • 48349105653 scopus 로고    scopus 로고
    • Synopsys, Inc, Online
    • Synopsys, Inc.: RTL Synthesis. Online (2008)
    • (2008) RTL Synthesis
  • 12
    • 61649088642 scopus 로고    scopus 로고
    • Mentor Graphics: ModelSim 5.8e. Online (2008)
    • Mentor Graphics: ModelSim 5.8e. Online (2008)
  • 13
    • 61649108371 scopus 로고    scopus 로고
    • Advanced RISC Machines: ARM946E-S. Online (2008)
    • Advanced RISC Machines: ARM946E-S. Online (2008)
  • 14
    • 61649087463 scopus 로고    scopus 로고
    • ARC International: ARC EP20 Core. Online (2008)
    • ARC International: ARC EP20 Core. Online (2008)
  • 15
    • 61649092374 scopus 로고    scopus 로고
    • Silicon Hive: HiveFlex CSP2000 Series, Communication Signal Processor. Online (2008)
    • Silicon Hive: HiveFlex CSP2000 Series, Communication Signal Processor. Online (2008)
  • 16
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    • Texas Instrumets: Data sheet: TMS320C6454 Fixed-Point Digital Signal Processor (Rev. D). Online (2008)
    • Texas Instrumets: Data sheet: TMS320C6454 Fixed-Point Digital Signal Processor (Rev. D). Online (2008)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.