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Volumn , Issue , 2004, Pages 7-11

A novel pipelined fast fourier transform architecture for double rate OFDM systems

Author keywords

FFT IFFT; Multiplier; OFDM; Processing element; Radix 2; Throughput

Indexed keywords

FFT/IFFT; MULTIPLIER; PROCESSING ELEMENTS; RADIX-2;

EID: 17044424210     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2005.1579830     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 2
    • 0031623618 scopus 로고    scopus 로고
    • A new VLSI-oriented FFT algorithm and implementation
    • Jun.
    • L. Jia, Y. Gao, Jouni and H. Tenhunen, "A new VLSI-oriented FFT algorithm and implementation," IEEE International ASIC Conf., pp. 337 - 341, Jun. 1998.
    • (1998) IEEE International ASIC Conf. , pp. 337-341
    • Jia, L.1    Gao, Y.2    Jouni3    Tenhunen, H.4
  • 3
    • 85008026861 scopus 로고
    • A pipelined, high-precision FFT architecture
    • Aug.
    • T. M. Hopkinson and G. M. Butler, "A pipelined, high-precision FFT architecture," Proc. the 35th Midwest Symposium, vol. 2, pp. 835 - 838, Aug. 1992.
    • (1992) Proc. the 35th Midwest Symposium , vol.2 , pp. 835-838
    • Hopkinson, T.M.1    Butler, G.M.2
  • 4
    • 0018467053 scopus 로고
    • Very fast Fourier transform algorithms for hardware implementation
    • May
    • A. M. Despain, "Very fast Fourier transform algorithms for hardware implementation," IEEE Trans. Computers, vol. C-28, pp. 333 - 341, May 1979.
    • (1979) IEEE Trans. Computers , vol.C-28 , pp. 333-341
    • Despain, A.M.1
  • 5
    • 0032217939 scopus 로고    scopus 로고
    • Designing pipeline FFT processor for OFDM (de)modulation
    • Oct.
    • S. He and M. Torkelson, "Designing pipeline FFT processor for OFDM (de)modulation," Signals, Systems, and Electronics, pp. 257 - 262, Oct. 1998.
    • (1998) Signals, Systems, and Electronics , pp. 257-262
    • He, S.1    Torkelson, M.2
  • 6
    • 0031633013 scopus 로고    scopus 로고
    • Design and implementation of a 1024-point pipeline FFT processor
    • May
    • S. He and M. Torkelson, "Design and implementation of a 1024-point pipeline FFT processor," IEEE Custom Integrated Circuits Conference, pp. 131 - 134, May. 1998.
    • (1998) IEEE Custom Integrated Circuits Conference , pp. 131-134
    • He, S.1    Torkelson, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.