A cost analysis framework for multi-core systems with spares

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Shamshiri, Saeed ^a   Lisherness, Peter ^a   Pan, Sung Jui ^a   Cheng, Kwang Ting ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BURN-IN; CHIP SIZES; COST ANALYSIS; DEFECT COVERAGE; FAILURE RATE; HIGH QUALITY; IN-FIELD; KEY PARAMETERS; MANUFACTURING TESTING; MULTI-CORE SYSTEMS; MULTICORE CHIPS; OVERALL COSTS;

COST ACCOUNTING; COSTS; MICROPROCESSOR CHIPS;

COST BENEFIT ANALYSIS;

EID: 67249139250     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700562     Document Type: Conference Paper

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