Adaptive power management for the on-chip communication network

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 649-656

  Guang, Liang ^a   Jantsch, Axel ^b  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; NETWORK ROUTING; SWITCHING FUNCTIONS; TELECOMMUNICATION TRAFFIC;

ADAPTIVE POWER MANAGEMENT; DEFLECTIVE ROUTING NETWORK; DYNAMIC FREQUENCY; POWER EFFICIENCY;

TELECOMMUNICATION NETWORKS;

EID: 34547977723     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.21     Document Type: Conference Paper

References (19)

1. N. Jha, "Low power system scheduling and synthesis, embedded tutorial," in Proceedings of the International Conference on Computer Aided Design, November 2001, pp. 259-263.
2. V. Raghunathan, M. B. Srivastava, and R. K. Gupta, "A survey of techniques for energy effi cient on-chip communication," in Proceedings of the Design Automation Conference, June 2003, pp. 900-905.
3. L. Shang, L.-S. Peh, and N. K. Jha, "Power-efficient interconnection networks: Dynamic voltage scaling with links," Computer Architecture Letters, vol. 1, May 2002.
4. A. Vitkovski, R. Haukilahti, A. Jantsch, and E. Nilsson, "Low-power and error coding for network-on-chip traffi c," in Proceedings of the IEEE NorChip Conference, November 2004. [Online]. Available: http://www.imit.kth.se/ axel/papers/2004/NorChip-arseni-vitkowski.pdf
5. D. Pamunuwa, J. Öberg, L.-R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen, "A study on the implementation of 2-D mesh based networks on chip in the nanoregime," Integration - The VLSI Journal, vol. 38, no. 1, pp. 3-17, October 2004.
6. S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä, and A. Hemani, "A network on chip architecture and design methodology," in Proceedings of IEEE Computer Society Annual Symposium on VLSI, April 2002. [Online]. Available: http://www.imit.kth.se/ axel/papers/2002/ISVLSI.pdf
7. M. Millberg, E. Nilsson, R. Thid, S. Kumar, and A. Jantsch, "The Nostrum backbone - a communication protocol stack for networks on chip," in Proceedings of the VLSI Design Conference, Mumbai, India, January 2004. [Online]. Available: http://www.imit.kth.se/ axel/papers/2004/VLSI-Millberg.pdf
8. M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip," in Proceedings of the Design Automation and Test Europe Conference (DATE), February 2004. [Online]. Available: http://www.imit.kth.se/ axel/papers/2004/DATE-Millberg.pdf
9. E. Nilsson and J. Oberg, "Reducing peak power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking," in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, September 2004. [Online]. Available: http://www.imit.kth. se/ axel/papers/2004/CODES+ISSS-Erland.pdf
10. G. Wei, J. Kim, D. Liu, S. Sidiropoulos, and M. Horowitz, "A variabla frequency parallel I/O interface with adaptive power supply regulation," J. of Solid State Circuits, vol. 35, no. 11, pp. 1600-1610, Nov. 2000.
11. J. Kim and M. A. Horowitz, "Adaptive supply serial links with subIv operation and per-pin clock recovery," in Proceedings of the IEEE International Solid State Circuits Conference, 2002, pp. 268-269.
12. E. J. Kim, K. H. Yum, G. M. Link, C. R. Das, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Energy optimization techniques in cluster interconnects," in International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003.
13. V. Soteriou and L.-S. Peh, "Design-space exploration of power-aware on/off interconnection networks," in Proceedings of the 22nd International Conference on Computer Design (ICCD), October 2004.
14. F. Worm, P. Ienne, P. Thiran, , and G. D. Micheli, "A robust selfcalibrating transmission scheme for on-chip networks," IEEE Transactions on very large scale integration (VLSI) systems, vol. 12, no. 12, pp. 1360-1373, December 2004.
15. A. J. Stratakos, "High-efficiency low-voltage DC-DC conversion for portable applications," Ph.D. dissertation, University of California, Berkeley, 1998.
16. T. D. Burd and R. W. Brodersen, "Design issues for dynamic voltage scaling," in Proceedings International Symposium on Low Power Electronics and Design, Rapallo, Italy, 2000, pp. 9 - 14.
17. W. J. Dally and J. W. Poulton, Digitial Systems Engineering. New York: CUP, 1998.
18. R. Jejurikar, C. Pereira, and R. K. Gupta, "Leakage aware dynamic voltage scaling for real time embedded systems," CECS, Tech. Rep. 03-35, 2003.
19. M. Wang, T. M. Madhyastha, N. H. Chan, S. Papadimitriou, and C. Faloutsos, "Data mining meets performance evaluation: Fast algorithms for modeling bursty traffic," in ICDE, 2002. [Online]. Available: citeseer.ist.psu.edu/article/wang01data.html