Autonomous DVFS on supply islands for energy-constrained NoC communication

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5455 LNCS, Issue , 2009, Pages 183-194

  Guang, Liang ^a   Nigussie, Ethiopia ^a   Koskinen, Lauri ^b   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

^b AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION ENERGIES; ENERGY-CONSTRAINED; LOW ENERGIES; LOWER ENERGIES; MANY CORES; NETWORK CONDITIONS; NETWORK ON CHIPS; QUANTITATIVE SIMULATIONS; SPATIAL NETWORKS; SUPPLY MANAGEMENTS; TRAFFIC PATTERNS;

ELECTRIC NETWORK TOPOLOGY; INTERNET;

ENERGY EFFICIENCY;

EID: 63449085782     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-00454-4_19     Document Type: Conference Paper

References (28)

1. Asanovic, K., Bodik, R., Catanzaro, B.C., Gebis, J.J., Husbands, P., Keutzer, K., Patterson, D.A., Plishker, W.L., Shalf, J., Williams, S.W., Yelick, K.A.: The landscape of parallel computing research: A view from berkeley. Technical Report UCB/EECS-2006-183, EECS, Uni. of California, Berkeley (December 2006)
2. Rabaey, J.M.: Scaling the power wall: Revisiting the low-power design rules. In: Keynote speech at SoC 2007 Symposium, Tampere (November 2007)
3. Dally, W.: Computer architecture is all about interconnect. In: HPCA ( International Symposium on High Performance Computer Architecture) Panel (February 2002)
4. Shang, L., Peh, L.S., Jha, N.: Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proc. Ninth International Symposium on High-Performance Computer Architecture HPCA-9 2003, pp. 91-102 (2003)
5. Yuan Tian, E., Ekici, F.O.: Energy-constrained task mapping and scheduling in wireless sensor networks. In: IEEE International Conference on Mobile Adhoc and Sensor Systems Conference, p. 218 (2005)
6. Liang, G., Jantsch, A.: Adaptive power management for the on-chip communication network. In: Proc. 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools DSD 2006, pp. 649-656 (2006)
7. Luo, J., Jha, N.K., Peh, L.S.: Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems. IEEE transactions on VLSI systems 15(4), 427-437 (2007)
8. Hazucha, P., Schrom, G., Hahn, J., Bloechel, B., Hack, P., Dermer, G., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.: A 233-mhz 80%-87% efficient four-phase dc-dc converter utilizing air-core inductors on package. IEEE Journal of Solid-State Circuits 40(4), 838-845 (2005)
9. Kim, W., Gupta, M.S., Wei, G.Y., Brooks, D.: System level analysis of fast, per-core dvfs using on-chip switching regulators. In: International symposium on high-performance computer architecture (February 2008)
10. Leung, L.F., Tsui, C.Y.: Energy-aware synthesis of networks-on-chip implemented with voltage islands. In: Proc. 44th ACM/IEEE Design Automation Conference DAC 2007, pp. 128-131 (2007)
11. Hu, J., Shin, Y., Dhanwada, N., Marculescu, R.: Architecting voltage islands in core-based system-on-a-chip designs. In: ISLPED 2004: Proceedings of the 2004 international symposium on Low power electronics and design, pp. 180-185. ACM, New York (2004)
12. Wu, H., Liu, I.M., Wong, M., Wang, Y.: Post-placement voltage island generation under performance requirement. In: Proc. ICC AD 2005, IEEE/ACM International Conference on Computer-Aided Design, pp. 309-316 (2005)
13. Ogras, U., Marculescu, R., Choudhary, P., Marculescu, D.: Voltage-frequency island partitioning for gals-based networks-on-chip. In: Proc. 44th ACM/IEEE Design Automation Conference DAC 2007, pp. 110-115 (2007)
14. Lackey, D., Zuchowski, P., Bednar, T., Stout, D., Gould, S., Cohn, J.: Managing power and performance for system-on-chip designs using voltage islands. In: Proc. IEEE/ACM International Conference on Computer Aided Design ICCAD 2002, pp. 195-202 (2002)
15. Wang, H.S., Zhu, X., Peh, L.S., Malik, S.: Orion: a power-performance simulator for interconnection networks. In: Proc. 35th Annual IEEE/ACM International Symposium on (MICRO-35) Microarchitecture, pp. 294-305 (2002)
16. Hu, J., Marculescu, R.: Energy and performance-aware mapping for regular noc architectures. IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems 24(4), 551-562 (2005)
17. Wibben, J., Harjani, R.: A high efficiency dc-dc converter using 2nh on-chip inductors. In: Proc. IEEE Symposium on VLSI Circuits, pp. 22-23 (2007)
18. Ogras, U.Y., Marculescu, R., Choudhary, P., Marculescu, D.: Voltage-frequency island partitioning for gals-based networks-on-chip. In: DAC 2007: Proceedings of the 44th annual conference on Design automation, pp. 110-115. ACM, New York (2007)
19. Sengupta, D., Saleh, R.: Application-driven floorplan-aware voltage island design. In: Proc. 45th ACM/IEEE Design Automation Conference DAC 2008, pp. 155-160 (2008)
20. Jesshope, C, Miller, P., Yantchev, J.: High performance communications in processor networks. In: Proc. 16th Annual International Symposium on Computer Architecture, 28 May - 1 June, 1989, pp. 150-157 (1989)
21. Wang, H.: A detailed architectural-level power model for router buffers, crossbars and arbiters. Technical report, Department of Electrical Engineering, Princeton University (2004)
22. Sakurai, T., Newton, A.: Alpha-power law mosfet model and its applications to cmos inverter delay and other formulas. IEEE Journal of solid-state circuits 25(2), 584-594 (1990)
23. Stratakos, A.J.: High-efficiency iow-voltage DC-DC conversion for portable applications. PhD thesis, University of California, Berkeley (1998)
24. Wang, M., Madhyastha, T., Chan, N.H., Papadimitriou, S., Faloutsos, C: Data mining meets performance evaluation: fast algorithms for modeling bursty traffic. In: Proc. 18th International Conference on Data Engineering, pp. 507-516 (2002)
25. Lu, Z., Jantsch, A., Salminen, E., Grecu, C: Network-on-chip benchmarking specification part 2: Microbenchmark specification version 1.0. Technical report, OCP fnternationaf Partnership Association, fnc. (May 2008)
26. Tierno, J., Rylyakov, A., Friedman, D.: A wide power supply range, wide tuning range, all static cmos all digital pll in 65 nm soi. IEEE Journal of Solid-State Circuits 43(1), 42-51 (2008)
27. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C, Hoskote, Y., Borkar, N., Borkar, S.: An 80-tife sub-100-w teraflops processor in 65-nm cmos. IEEE Journal of Solid-State Circuits 43(1), 29-41 (2008)
28. Wang, A., Chandrakasan, A.: A 180mv fft processor using subthreshold circuit techniques, In: Proc. Digest of Technical Papers Solid-State Circuits Conference ISSCC, IEEE fnternational, vol. 1, pp. 292-529 (2004)