Exploring the design space of self-regulating power-aware on/off interconnection networks

IEEE Transactions on Parallel and Distributed Systems

Volumn 18, Issue 3, 2007, Pages 393-408

  Soteriou, Vassos ^a   Peh, Li Shiuan ^a  

^a Princeton University   (United States)

Author keywords

Communication link; Interconnection networks; Low power design; Network topology; On off mechanism; Routing algorithm

Indexed keywords

BLOCKING PROBABILITY; COMPUTER SIMULATION; CONTROL SYSTEM SYNTHESIS; MICROPROCESSOR CHIPS; ON-OFF CONTROL SYSTEMS; ROUTING ALGORITHMS; TELECOMMUNICATION LINKS; TOPOLOGY;

CHIP-TO-CHIP NETWORK; LOW-POWER DESIGN; POWER-AWARE NETWORKS;

INTERCONNECTION NETWORKS;

EID: 33947389289     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2007.43     Document Type: Article

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