A 167-processor computational platform in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1130-1144

  Truong, Dean N ^a   Cheng, Wayne H ^f   Mohsenin, Tinoosh ^a   Yu, Zhiyi ^b   Jacobson, Anthony T ^c   Landge, Gouri ^a,d   Meeuwsen, Michael J ^d   Watnik, Christine ^a,d   Tran, Anh T ^a   Xiao, Zhibin ^a   Work, Eric W ^f   Webb, Jeremy W ^a,e   Mejia, Paul V ^a   Baas, Bevan M ^a  

^a University of California   (United States)

^b FUDAN UNIVERSITY   (China)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d INTEL CORPORATION   (United States)

^e Centellax Inc   (United States)

^f Intel Digital Enterprise Group ^*

Author keywords

65 nm CMOS; Array processor; Digital signal processing; Digital signal processor; DSP; DVFS; dynamic voltage and frequency scaling; Embedded; GALS; Globally asynchronous locally synchronous; Heterogeneous; Homogeneous; Many core; Multi core; multimedia; Network on chip; NoC

Indexed keywords

65 NM CMOS; ARRAY PROCESSOR; DIGITAL SIGNAL PROCESSOR; DSP; DVFS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; EMBEDDED; GALS; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; HETEROGENEOUS; HOMOGENEOUS; MANY-CORE; MULTI-CORE; MULTIMEDIA; NETWORK ON CHIP; NOC;

DIGITAL SIGNAL PROCESSING; DISTRIBUTED COMPUTER SYSTEMS; ELECTRIC NETWORK TOPOLOGY; ELECTRON ENERGY LOSS SPECTROSCOPY; ENERGY DISSIPATION; ENERGY DISSIPATORS; MICROPROCESSOR CHIPS; SIGNAL ENCODING; SIGNAL PROCESSING; SPEED CONTROL; SWITCHING CIRCUITS; VOLTAGE CONTROL;

DIGITAL SIGNAL PROCESSORS;

EID: 63449130720     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2013772     Document Type: Conference Paper

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