Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 2, 2008, Pages 134-143

  Zipf, Peter ^a,b,c  

^a IEEE

^b UNIVERSITY OF SIEGEN   (Germany)

^c DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Distributed self testing; Dynamically reconfigurable architectures; Logic circuit fault diagnosis; Logic circuit fault tolerance

Indexed keywords

COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROMETERS; PRODUCT DESIGN;

DISTRIBUTED SELF TESTING; LOGIC CIRCUIT FAULT DIAGNOSIS;

FAULT TOLERANCE;

EID: 38349122464     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.912028     Document Type: Article

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