Measurement and analysis of variability in 45nm strained-Si CMOS technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 129-132

  Pang, Liang Teck ^a   Nikolić, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGIES; CMOS CIRCUITS; LOW POWERS; MEASUREMENT AND ANALYSIS; ON CHIPS; SI CMOS; STRAIN EFFECTS; SYSTEMATIC VARIATIONS; TRANSISTOR LEAKAGES;

CMOS INTEGRATED CIRCUITS; DIES; INTEGRATED CIRCUITS; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS;

ELECTRIC NETWORK ANALYSIS;

EID: 57849105538     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672038     Document Type: Conference Paper

References (7)

1. L.T. Pang, B. Nikolić, "Impact of layout on 90nm process parameter fluctuations," VLSI Circ. Dig., 2006, pp 69-70
2. E. Josse et al., "A Cost-Effective Low Power Platform for the 45-nm Technology Node," International Electron Devices Meeting, IEDM 2006, pp 14
3. C. Le Cam et al., "A Low Cost Drive Current Enhancement Technique Using Shallow Trench Isolation Induced Stress for 45-nm Node," VLSI Tech. Dig., 2006, pp 82-83
4. B. Le Oratiet et al, "Process Control for 45nm CMOS logic Gate Patterning," Proceedings SPIE, Volume 6922, March 2008
5. R. A. Bianchi, G. Bouche, O. Roux-dit-Buisson, "Accurate Modeling of Trench Isolation. Induced Mechanical Stress Effects on MOSFET Electrical Performance," International Electron Devices Meeting, IEDM 2002, pp 117-120
6. H. Tuinhout, M. Pelgrom, R. Penning de Vries and M. Vertregt, "Effects of Metal Coverage on MOSFET Matching," International Electron Devices Meeting, IEDM: 1996, pp 735-738
7. I. Ohkura et al, "Gate isolation - A novel basic cell configuration for CMOS gate arrays," Proc. IEEE 1982 CICC, May 1982, pp 307-310