Analysis and decomposition of spatial variation in integrated circuit processes and devices

IEEE Transactions on Semiconductor Manufacturing

Volumn 10, Issue 1, 1997, Pages 24-41

  Stine, Brian E ^a,b   Boning, Duane S ^a,b   Chung, James E ^a,b  

^a IEEE   (United States)

^b USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FOURIER TRANSFORMS; INTEGRATED CIRCUIT LAYOUT; INTERPOLATION; PROCESS CONTROL; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR MATERIALS;

DIE LEVEL; SAMPLING REQUIREMENTS; SPATIAL VARIATION ANALYSIS; SPATIAL VARIATION DECOMPOSITION; SPECTRAL INTERPOLATION; WAFER DIE INTERACTION; WAFER LEVEL;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0031077147     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.554480     Document Type: Article

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