Modeling within-die spatial correlation effects for process-design co-optimization

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 516-521

  Friedberg, Paul ^a   Cao, Yu ^a   Cain, Jason ^a   Wang, Ruth ^a   Rabaey, Jan ^a   Spanos, Costas ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; CO-OPTIMIZATION; DEVICE PARAMETERS; GATE LENGTH; MANUFACTURING VARIATION; SPATIAL CORRELATION MODELS; SPATIAL CORRELATIONS; VERTICAL SEPARATION;

ELECTRIC NETWORK ANALYSIS;

DESIGN;

EID: 84886673851     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.82     Document Type: Conference Paper

References (9)

1. B. E. Stine, D. S. Boning, and J. E. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices," IEEE TSM, vol. 10, no. 1, Feb. 1997.
2. International Technology Roadmap for Semiconductors, 2003.
3. S. Nassif, "Design for manufacturability in DSM technologies," IEEE International Symposium on Quality Electronics Design, pp. 451-454, 2000.
4. X. Niu, N. Jakatdar, J. Bao, and C. Spanos, "Specular Spectroscopic Scatterometry," IEEE Transactions on Semiconductor Manufacturing, vol. 14, no. 2, pp. 97-111, 2001.
5. Y. Cao, et al., "Design sensitivities to variability: extrapolations and assessments in nanometer VLSI," IEEE International ASIC/SoC Conference, pp. 411-415, 2002.
6. M. Orshansky, et al., "Impact of spatial intra-chip gate length variability on the performance of high speed digital circuits," IEEE Transactions on Computer-Aided Design, vol. 21, pp. 544-553, May 2002.
7. J. Cain and C. Spanos, "Electrical linewidth metrology for systematic CD variation characterization and causal analysis," Metrology, Inspection, and Process Control for Microlithography XVII, Proceedings of SPIE vol. 5038, pp. 350-361, 2003.
8. Y. Cao, et al., "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," IEEE Custom Integrated Circuits Conference, pp. 201-204, 2000.
9. J. van Schoot, et al, "CD uniformity improvement by active scanner corrections," Optical Microlithography XV, Proceedings of SPIE vol. 4691, pp. 304-312, 2002.