Random sampling for on-chip characterization of standard-cell propagation delay

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 41-45

  Maggioni, S ^a   Veggetti, A ^a   Bogliolo, A ^b   Croce, L ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF URBINO   (Italy)

Author keywords

CMOS process; CMOS technology; Logic; Propagation delay; Sampling methods; Semiconductor device measurement; Semiconductor device modeling; Standards development; Testing; Timing

Indexed keywords

ADDERS; CHARACTERIZATION; CMOS INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; STANDARDS; TESTING;

CMOS PROCESSS; CMOS TECHNOLOGY; LOGIC; PROPAGATION DELAYS; SAMPLING METHOD; SEMICONDUCTOR DEVICE MEASUREMENTS; STANDARDS DEVELOPMENT; TIMING;

STANDARDIZATION;

EID: 84942092182     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194707     Document Type: Conference Paper

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