Duty cycle measurement and correction using a random sampling technique

Midwest Symposium on Circuits and Systems

Volumn 2005, Issue , 2005, Pages 1043-1046

  Bhatti, Hashed Zafar ^a   Denneau, Monty ^b   Draper, Jeff ^c  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY RESOLUTION; DUTY CYCLE MEASUREMENT; PIPELINED CIRCUITS; RANDOM SAMPLING TECHNIQUE;

ANALOG TO DIGITAL CONVERSION; COMPUTER SIMULATION; ELECTRIC VARIABLES MEASUREMENT; ERROR ANALYSIS; MICROPROCESSOR CHIPS; RANDOM PROCESSES; VLSI CIRCUITS;

ELECTRIC CLOCKS;

EID: 33847136857     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2005.1594283     Document Type: Conference Paper

References (15)

1. Spiegel, Schiller, Srinivasan, "Theory and Problems of Probability and Statistics"; 2nd Edition, McGraw Hill.
2. Kihyuk Sung; Lee-Sup Kim, "A high-resolution synchronous mirror delay using successive approximation register", JSSC, IEEE, Volume: 39, Issue: 11, Nov. 2004 Pages: 1997 - 2004.
3. Kuo-Hsing Cheng et al, "A phase-locked pulse width control loop with programmable duty cycle", Advanced System Integrated Circuits 2004. IEEE Asia-Pacific Conference.
4. Yi-Ming Wang et al, "An all-digital 50% duty-cycle corrector", International Symposium on Circuits and Systems 2004, Volume: 2 , 23-26 May 2004
5. Po-Hui Yang, Jinn-Shyan Wang, "Low-voltage pulsewidth control loops for SOC applications", JSSC, IEEE, Volume: 37 , Issue: 10 , Oct. 2002 Pages: 1348-1351
6. T. Gawa et al, "A 50% duty-cycle correction circuit for PLL output", IEEE International Symposium on Circuits and Systems 2002, Volume: 4, 26-29 May 2002.
7. K. Nakamura, et al, 'A CMOS 50% duty cycle repeater using complementary phase blending", Symposium on VLSI Circuits, 2000. Digest of Technical Papers. June 2000.
8. T.Saeki, Y. Nakaoka, M. Fujita, "A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay", IEEE Journal of Solid-State Circuits, Nov. 1996.
9. J. Rabaey, "Digital Integrated Circuits". Englewood Cliffs, NJ: Prentice- Hall, 1996.
10. J.-N. Seizovic, "Pipeline synchronization," Proc. IEEE ASYNC, 1994.
11. A. J. Johansson, H. Floberg, "Random number generation by chaotic double scroll oscillator on chip; IEEE International Symposium on Circuits and Systems, 1999.
12. G. Chen and T. Ueta, "Chaos in Circuits and Systems", ed 2002 (Singapore: World Scientific)
13. G.M. Bernstein, M.A. Lieberman, "Secure random number generation using chaotic circuits", IEEE Transactions on Circuits and Systems, Volume: 37, Issue: 9 , Sept. 1990 Pages: 1157 - 1164
14. Fengling Han et al, "n-scroll chaotic oscillators by second-order systems and double-hysteresis blocks", Elect Ltrs, Volume: 39 , Issue: 23 , 13 Nov. 2003 Pages: 1636-8
15. B. Vizvari, O. Kolumban, "Quality evaluation of random numbers generated by chaotic sampling phase-locked loops" IEEE Transactions on Circuits and Systems, Volume: 45 , Issue: 3 , March 1998.