A high speed and low power phase-frequency detector and charge - Pump

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1999-January, Issue , 1999, Pages 269-272

  Lee, Won Hyo ^a   Cho, Jun Dong ^a   Lee, Sung Dae ^b  

^a Sungkyunkwan University   (South Korea)

^b Ansan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE PUMP CIRCUITS; CLOCKS; COMPUTER AIDED DESIGN; FLIP FLOP CIRCUITS; PHASE LOCKED LOOPS;

CHARGE AMPLIFIERS; CHARGE PUMP PLL; CMOS TECHNOLOGY; FREQUENCY ERRORS; PHASE CHARACTERISTIC; PHASE FREQUENCY DETECTORS; PHASE SENSITIVITY; PRESCALER CIRCUITS;

PHASE COMPARATORS;

EID: 85074755251     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.1999.760011     Document Type: Conference Paper

References (8)

1. R.E.Best, Phase - - Locked Loops, 2nd ed. New York, NY: McGraw - Hill, 1993
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3. Henrik O. Johansson, "A Simple Precharged CMOS Phase Frequency Detector.," IEEE Journal of Solid State Circuits, vol. 33, no.2, pp. 295 - 259, Feb. 1998.
4. Ian A. Young, Jeffery K. Greason and Keng L. Wong, " A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors," IEEE Journal of Solid State Circuits, VOL.. SC - 27, pp. 1559 - 1607, Nov. 1992.
5. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, IEEE PRESS.
6. Mihai Banu, and Alfred Dunlop," A 660Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst - Mode Transmission," ISSCC Dig. Tech. Papers, pp. 102 - 103, Feb. 1993.
7. Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1993.
8. Hiroyasu Yoshizawa, Kenji Taniguchi, Hiroyuki Shirahama, and Kenichi Nakashi, "A Low Power 622MHz CMOS Phase - Locked Loop with Source Coupled VCO and Dynamic PFD", IEICE Trans. Fundamentals. Vol. F80.ANo.6pp. 1015-1020. June 1997.