Lack of spatial correlation in mosfet threshold voltage variation and implications for voltage scaling

IEEE Transactions on Semiconductor Manufacturing

Volumn 22, Issue 2, 2009, Pages 245-255

  Drego, Nigel ^a   Chandrakasan, Anantha ^a   Boning, Duane ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

Spatial correlation; threshold voltage; Variation

Indexed keywords

CMOS PROCESS; DIGITAL LOGIC CIRCUIT; KEY ISSUES; LARGE ARRAYS; MONTE CARLO; MOSFET THRESHOLD VOLTAGE VARIATION; PRIMARY MECHANISM; PROCESS TECHNOLOGIES; RANDOM DOPANT FLUCTUATION; SPATIAL CORRELATION; SPATIAL CORRELATIONS; SPATIALLY CORRELATED CHANNELS; SUBTHRESHOLD LOGIC; TEST-STRUCTURE; TYPE ANALYSIS; VARIATION; VARIATION PATTERN; VOLTAGE-SCALING; WITHIN DIES;

DIES; DIGITAL CIRCUITS; LOGIC CIRCUITS; MOSFET DEVICES; SWITCHING CIRCUITS; THRESHOLD VOLTAGE;

CORRELATION METHODS;

EID: 67649277688     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2009.2017645     Document Type: Article

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