메뉴 건너뛰기




Volumn 9, Issue 3, 2009, Pages 166-173

Reliability characteristics of La-doped high-k/metal gate nMOSFETs

Author keywords

La doped high k metal gate nMOSFETs

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; GATE DIELECTRICS; HAFNIUM OXIDES; HIGH-K DIELECTRIC; LANTHANUM OXIDES; RELIABILITY; THRESHOLD VOLTAGE;

EID: 70350685962     PISSN: 15981657     EISSN: None     Source Type: Journal    
DOI: 10.5573/JSTS.2009.9.3.166     Document Type: Article
Times cited : (4)

References (32)
  • 5
    • 45249084302 scopus 로고    scopus 로고
    • Electrical characterization methodologies for the assessment of high-? gate dielectric stacks
    • Washington, DC
    • C. D. Young, G. Bersuker, D. Heh, A. Neugroschel, R. Choi, C. Y. Kang, J. Tun, and B. H. Lee, "Electrical characterization methodologies for the assessment of high-? gate dielectric stacks," in ECS Transactions, Washington, DC, 2007, pp. 335-346.
    • (2007) ECS Transactions , pp. 335-346
    • Young, C.D.1    Bersuker, G.2    Heh, D.3    Neugroschel, A.4    Choi, R.5    Kang, C.Y.6    Tun, J.7    Lee, B.H.8
  • 10
    • 4544326573 scopus 로고    scopus 로고
    • Effects of barrier height (F{cyrillic}B) and the nature of Bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology
    • Y. H. Kim, R. Choi, R. Jha, J. H. Lee, V. Misra, and J. C. Lee, "Effects of barrier height (F{cyrillic}B) and the nature of Bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology," in Digest of Technical Papers - Symposium on VLSI Technology, 2004, pp.138-139.
    • (2004) Digest of Technical Papers - Symposium on VLSI Technology , pp. 138-139
    • Kim, Y.H.1    Choi, R.2    Jha, R.3    Lee, J.H.4    Misra, V.5    Lee, J.C.6
  • 13
    • 3943106164 scopus 로고    scopus 로고
    • A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/by using HfN replacement gate
    • C. Y. Ren, H. Y. Kang, J. F. Wang, X. P. Ma, H. Chan, D. S. H. Li, and M. F. Kwong, "A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/by using HfN replacement gate," Electron Device Letters, IEEE, Vol. 25, pp. 580-582, 2004.
    • (2004) Electron Device Letters, IEEE , vol.25 , pp. 580-582
    • Ren, C.Y.1    Kang, H.Y.2    Wang, J.F.3    Ma, X.P.4    Chan, H.5    Li, D.S.H.6    Kwong, M.F.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.