-
1
-
-
50249185641
-
A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging
-
K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Rarade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," in Technical Digest - International Electron Devices Meeting, IEDM, 2007, pp. 247-250.
-
(2007)
Technical Digest - International Electron Devices Meeting, IEDM
, pp. 247-250
-
-
Mistry, K.1
Allen, C.2
Auth, C.3
Beattie, B.4
Bergstrom, D.5
Bost, M.6
Brazier, M.7
Buehler, M.8
Cappellani, A.9
Chau, R.10
Choi, C.H.11
Ding, G.12
Fischer, K.13
Ghani, T.14
Grover, R.15
Han, W.16
Hanken, D.17
Hattendorf, M.18
He, J.19
Hicks, J.20
Huessner, R.21
Ingerly, D.22
Jain, P.23
James, R.24
Jong, L.25
Joshi, S.26
Kenyon, C.27
Kuhn, K.28
Lee, K.29
Liu, H.30
Maiz, J.31
McIntyre, B.32
Moon, P.33
Neirynck, J.34
Pae, S.35
Parker, C.36
Parsons, D.37
Prasad, C.38
Pipes, L.39
Prince, M.40
Rarade, P.41
Reynolds, T.42
Sandford, J.43
Shifren, L.44
Sebastian, J.45
Seiple, J.46
Simon, D.47
Sivakumar, S.48
Smith, P.49
Thomas, C.50
Troeger, T.51
Vandervoorn, P.52
Williams, S.53
Zawadzki, K.54
more..
-
2
-
-
35348909664
-
The high-k solution
-
M. T. Bohr, R. S. Chau, T. Ghani, and K. Mistry, "The high-k solution," IEEE Spectrum, Vol. 44, pp. 29-35, 2007.
-
(2007)
IEEE Spectrum
, vol.44
, pp. 29-35
-
-
Bohr, M.T.1
Chau, R.S.2
Ghani, T.3
Mistry, K.4
-
3
-
-
21644465398
-
Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)
-
B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, and S. C. Song, "Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)," Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 859-862, 2004.
-
(2004)
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
, pp. 859-862
-
-
Lee, B.H.1
Young, C.D.2
Choi, R.3
Sim, J.H.4
Bersuker, G.5
Kang, C.Y.6
Harris, R.7
Brown, G.A.8
Matthews, K.9
Song, S.C.10
-
4
-
-
21644482313
-
Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operation
-
San Francisco, CA
-
C. Y. Kang, R. Choi, J. H. Sim, C. Young, B. H. Lee, G. Bersuker, and J. C. Lee, "Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operation," in Technical Digest - International Electron Devices Meeting, IEDM, San Francisco, CA, 2004, pp. 485-488.
-
(2004)
Technical Digest - International Electron Devices Meeting, IEDM
, pp. 485-488
-
-
Kang, C.Y.1
Choi, R.2
Sim, J.H.3
Young, C.4
Lee, B.H.5
Bersuker, G.6
Lee, J.C.7
-
5
-
-
45249084302
-
Electrical characterization methodologies for the assessment of high-? gate dielectric stacks
-
Washington, DC
-
C. D. Young, G. Bersuker, D. Heh, A. Neugroschel, R. Choi, C. Y. Kang, J. Tun, and B. H. Lee, "Electrical characterization methodologies for the assessment of high-? gate dielectric stacks," in ECS Transactions, Washington, DC, 2007, pp. 335-346.
-
(2007)
ECS Transactions
, pp. 335-346
-
-
Young, C.D.1
Bersuker, G.2
Heh, D.3
Neugroschel, A.4
Choi, R.5
Kang, C.Y.6
Tun, J.7
Lee, B.H.8
-
6
-
-
0042172980
-
Charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes
-
A. Kerber, E. Cartier, R. Degraeve, P. J. Roussel, L. Pantisano, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes," IEEE Transactions on Electron Devices, Vol. 50, pp. 1261-1269, 2003.
-
(2003)
IEEE Transactions on Electron Devices
, vol.50
, pp. 1261-1269
-
-
Kerber, A.1
Cartier, E.2
Degraeve, R.3
Roussel, P.J.4
Pantisano, L.5
Kauerauf, T.6
Groeseneken, G.7
Maes, H.E.8
Schwalke, U.9
-
7
-
-
46649085890
-
Modulation of TiSiN effective work function using high-pressure postmetallization annealing in dilute oxygen ambient
-
J. Lee, H. Park, H. Choi, M. Hasan, M. Jo, M. Chang, B. H. Lee, C. S. Park, C. Y. Kang, and H. Hwang, "Modulation of TiSiN effective work function using high-pressure postmetallization annealing in dilute oxygen ambient," Applied Physics Letters, Vol. 92, 2008.
-
(2008)
Applied Physics Letters
, vol.92
-
-
Lee, J.1
Park, H.2
Choi, H.3
Hasan, M.4
Jo, M.5
Chang, M.6
Lee, B.H.7
Park, C.S.8
Kang, C.Y.9
Hwang, H.10
-
8
-
-
34249805888
-
Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-k and dual metal gate CMOS integration
-
S. C. Song, Z. B. Zhang, M. M. Hussain, C. Huffman, J. Barnett, S. H. Bae, H. J. Li, P. Majhi, C. S. Park, and B. S. Ju, "Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-k and dual metal gate CMOS integration," VLSI Symp. Tech. Dig, 2006.
-
(2006)
VLSI Symp. Tech. Dig
-
-
Song, S.C.1
Zhang, Z.B.2
Hussain, M.M.3
Huffman, C.4
Barnett, J.5
Bae, S.H.6
Li, H.J.7
Majhi, P.8
Park, C.S.9
Ju, B.S.10
-
9
-
-
34247166249
-
Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics
-
S. Abermann, J. Efavi, G. Sjöblom, M. Lemme, J. Olsson, and E. Bertagnolli, "Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics," Microelectronics Reliability, Vol. 47, pp. 536-539, 2007.
-
(2007)
Microelectronics Reliability
, vol.47
, pp. 536-539
-
-
Abermann, S.1
Efavi, J.2
Sjöblom, G.3
Lemme, M.4
Olsson, J.5
Bertagnolli, E.6
-
10
-
-
4544326573
-
Effects of barrier height (F{cyrillic}B) and the nature of Bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology
-
Y. H. Kim, R. Choi, R. Jha, J. H. Lee, V. Misra, and J. C. Lee, "Effects of barrier height (F{cyrillic}B) and the nature of Bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology," in Digest of Technical Papers - Symposium on VLSI Technology, 2004, pp.138-139.
-
(2004)
Digest of Technical Papers - Symposium on VLSI Technology
, pp. 138-139
-
-
Kim, Y.H.1
Choi, R.2
Jha, R.3
Lee, J.H.4
Misra, V.5
Lee, J.C.6
-
11
-
-
21644439155
-
Impact of metal gate work function on nano CMOS device performance
-
Y. T. Hou, T. Low, B. Xu, M. F. Li, G. Samudra, and D. L. Kwong, "Impact of metal gate work function on nano CMOS device performance," in International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, 2004, pp. 57-60.
-
(2004)
International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
, pp. 57-60
-
-
Hou, Y.T.1
Low, T.2
Xu, B.3
Li, M.F.4
Samudra, G.5
Kwong, D.L.6
-
12
-
-
39549122434
-
Dual work function high-k/metal gate CMOS FinFETs
-
M. M. Hussain, C. Smith, P. Kalra, J. W. Yang, G. Gebara, B Sassman, P. Kirsch, P. Majhi, S. C. Song, R Harris, H. H. Tseng, and R. Jammy, "Dual work function high-k/metal gate CMOS FinFETs," in ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference, 2008, pp. 207-209.
-
(2008)
ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference
, pp. 207-209
-
-
Hussain, M.M.1
Smith, C.2
Kalra, P.3
Yang, J.W.4
Gebara, G.5
Sassman, B.6
Kirsch, P.7
Majhi, P.8
Song, S.C.9
Harris, R.10
Seng, H.H.11
Jammy, R.12
-
13
-
-
3943106164
-
A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/by using HfN replacement gate
-
C. Y. Ren, H. Y. Kang, J. F. Wang, X. P. Ma, H. Chan, D. S. H. Li, and M. F. Kwong, "A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/by using HfN replacement gate," Electron Device Letters, IEEE, Vol. 25, pp. 580-582, 2004.
-
(2004)
Electron Device Letters, IEEE
, vol.25
, pp. 580-582
-
-
Ren, C.Y.1
Kang, H.Y.2
Wang, J.F.3
Ma, X.P.4
Chan, H.5
Li, D.S.H.6
Kwong, M.F.7
-
14
-
-
46049102429
-
Band Edge n-MOSFETs with High-k/Metal Gate Stacks Scaled to EOT= 0.9 nm with Excellent Carrier Mobility and High Temperature Stability
-
P. D. Kirsch, M. A. Quevedo-Lopez, S. A. Krishnan, C. Krug, H. AlShareef, C. S. Park, R. Harris, N. Moumen, A. Neugroschel, and G. Bersuker, "Band Edge n-MOSFETs with High-k/Metal Gate Stacks Scaled to EOT= 0.9 nm with Excellent Carrier Mobility and High Temperature Stability," Electron Devices Meeting, 2006. IEDM'06. International, pp. 1-4, 2006.
-
(2006)
Electron Devices Meeting, 2006. IEDM'06. International
, pp. 1-4
-
-
Kirsch, P.D.1
Quevedo-Lopez, M.A.2
Krishnan, S.A.3
Krug, C.4
Alshareef, H.5
Park, C.S.6
Harris, R.7
Moumen, N.8
Neugroschel, A.9
Bersuker, G.10
-
15
-
-
40549096055
-
Dipole model explaining highk/ metal gate field effect transistor threshold voltage tuning
-
P. D. Kirsch, P. Sivasubramani, J. Huang, C. D. Young, M. A. Quevedo-Lopez, H. C. Wen, H. Alshareef, K. Choi, C. S. Park, K. Freeman, M. M. Hussain, G. Bersuker, H. R. Harris, P. Majhi, R. Choi, P. Lysaght, B. H. Lee, H. H. Tseng, R. Jammy, T. S. Boscke, D. J. Lichtenwalner, J. S. Jur, and A. I. Kingon, "Dipole model explaining highk/ metal gate field effect transistor threshold voltage tuning," Applied Physics Letters, Vol. 92, p. 092901, 2008.
-
(2008)
Applied Physics Letters
, vol.92
, pp. 092901
-
-
Kirsch, P.D.1
Sivasubramani, P.2
Huang, J.3
Young, C.D.4
Quevedo-Lopez, M.A.5
Wen, H.C.6
Alshareef, H.7
Choi, K.8
Park, C.S.9
Freeman, K.10
Hussain, M.M.11
Bersuker, G.12
Harris, H.R.13
Majhi, P.14
Choi, R.15
Lysaght, P.16
Lee, B.H.17
Tseng, H.H.18
Jammy, R.19
Boscke, T.S.20
Lichtenwalner, D.J.21
Jur, J.S.22
Kingon, A.I.23
more..
-
16
-
-
40949130851
-
Dipole moment model explaining nFET vt tuning utilizing La. Sc, Er, and Sr doped HfSiON dielectrics
-
P. Sivasubramani, T. S. Böscke, J. Huang, C. D. Young, P. D. Kirsch, S. A. Krishnan, M. A. Quevedo-Lopez, S. Govindarajan, B. S. Ju, H. R. Harris, D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, J. Kim, B. E. Gnade, R. M. Wallace, G. Bersuker, B. H. Lee, and R. Jammy, "Dipole moment model explaining nFET vt tuning utilizing La. Sc, Er, and Sr doped HfSiON dielectrics," in Digest of Technical Papers - Symposium on VLSI Technology, 2007, pp. 68-69.
-
(2007)
Digest of Technical Papers - Symposium on VLSI Technology
, pp. 68-69
-
-
Sivasubramani, P.1
Böscke, T.S.2
Huang, J.3
Young, C.D.4
Kirsch, P.D.5
Krishnan, S.A.6
Quevedo-Lopez, M.A.7
Govindarajan, S.8
Ju, B.S.9
Harris, H.R.10
Lichtenwalner, D.J.11
Jur, J.S.12
Kingon, A.I.13
Kim, J.14
Gnade, B.E.15
Wallace, R.M.16
Bersuker, G.17
Lee, B.H.18
Jammy, R.19
-
17
-
-
33645471189
-
Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs
-
X. P. Wang, L. Ming-Fu, C. Ren, X. F. Yu, C. Shen, H. H. Ma, A. Chin, C. X. Zhu, N. Jiang, M. B. Yu, and K. Dim-Lee, "Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs," Electron Device Letters, IEEE, vol. 27, pp. 31-33, 2006.
-
(2006)
Electron Device Letters, IEEE
, vol.27
, pp. 31-33
-
-
Wang, X.P.1
Ming-Fu, L.2
Ren, C.3
Yu, X.F.4
Shen, C.5
Ma, H.H.6
Chin, A.7
Zhu, C.X.8
Jiang, N.9
Yu, M.B.10
Dim-Lee, K.11
-
18
-
-
35948958613
-
Study of La-induced flat band voltage shift in metal/HfLaO x/SiO2/Si capacitors
-
Y. Yamamoto, K. Kita, K. Kyuno, and A. Toriumi, "Study of La-induced flat band voltage shift in metal/HfLaO x/SiO2/Si capacitors," Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 46, pp. 7251-7255, 2007.
-
(2007)
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
, vol.46
, pp. 7251-7255
-
-
Yamamoto, Y.1
Kita, K.2
Kyuno, K.3
Toriumi, A.4
-
19
-
-
34248589738
-
Dipole formation at direct-contact Hf O2 Si interface
-
Y. Abe, N. Miyata, Y. Shiraki, and T. Yasuda, "Dipole formation at direct-contact Hf O2 Si interface," Applied Physics Letters, Vol. 90, 2007.
-
(2007)
Applied Physics Letters
, vol.90
-
-
Abe, Y.1
Miyata, N.2
Shiraki, Y.3
Yasuda, T.4
-
20
-
-
51049095098
-
Reliability study of La[sub 2]O[sub 3] capped HfSiON highpermittivity n-type metal-oxide-semiconductor fieldeffect transistor devices with tantalum-rich electrodes
-
B. J. O. Sullivan, R. Mitsuhashi, G. Pourtois, M. Aoulaiche, M. Houssa, N. V. D. Heyden, T. Schram, Y. Harada, G. Groeseneken, P. Absil, S. Biesemans, T. Nakabayashi, A. Ikeda, and M. Niwa, "Reliability study of La[sub 2]O[sub 3] capped HfSiON highpermittivity n-type metal-oxide-semiconductor fieldeffect transistor devices with tantalum-rich electrodes," Journal of Applied Physics, Vol. 104, p. 044512, 2008.
-
(2008)
Journal of Applied Physics
, vol.104
, pp. 044512
-
-
Sullivan, B.J.O.1
Mitsuhashi, R.2
Pourtois, G.3
Aoulaiche, M.4
Houssa, M.5
Heyden, N.V.D.6
Schram, T.7
Harada, Y.8
Groeseneken, G.9
Absil, P.10
Biesemans, S.11
Nakabayashi, T.12
Ikeda, A.13
Niwa, M.14
-
21
-
-
67650283250
-
Reliability of thich oxides integrated with HfSiO~ x gate dielectric
-
B. H. Lee, C. Y. Kang, T. H. Lee, J. Barnett, R. Choi, S. C. Song, and R. Jammy, "Reliability of thich oxides integrated with HfSiO~ x gate dielectric," SOLID STATE DEVICES AND MATERIALS, Vol. 2006, p. 1122, 2006.
-
(2006)
SOLID STATE DEVICES AND MATERIALS
, vol.2006
, pp. 1122
-
-
Lee, B.H.1
Kang, C.Y.2
Lee, T.H.3
Barnett, J.4
Choi, R.5
Song, S.C.6
Jammy, R.7
-
22
-
-
33744796611
-
Quantitative analysis of contribution of initial traps to breakdown in HfAlOx/SiO2 stacked gate dielectrics
-
K. Okada, H. Ota, W. Mizubayashi, H. Satake, A. Ogawa, K. Iwamoto, T. Horikawa, T. Nabatame, and A. Toriumi, "Quantitative analysis of contribution of initial traps to breakdown in HfAlOx/SiO2 stacked gate dielectrics," in Digest of Technical Papers - Symposium on VLSI Technology, 2005, pp. 166-167.
-
(2005)
Digest of Technical Papers - Symposium on VLSI Technology
, pp. 166-167
-
-
Okada, K.1
Ota, H.2
Mizubayashi, W.3
Satake, H.4
Ogawa, A.5
Iwamoto, K.6
Horikawa, T.7
Nabatame, T.8
Toriumi, A.9
-
23
-
-
34548728065
-
Dielectric breakdown in high-K gate dielectrics - Mechanism and lifetime assessment
-
K. Okada, H. Ota, T. Nabatame, and A. Toriumi, "Dielectric breakdown in high-K gate dielectrics - Mechanism and lifetime assessment," in Annual Proceedings - Reliability Physics (Symposium), 2007, pp. 36-43.
-
(2007)
Annual Proceedings - Reliability Physics (Symposium)
, pp. 36-43
-
-
Okada, K.1
Ota, H.2
Nabatame, T.3
Toriumi, A.4
-
24
-
-
28744431635
-
High-k dielectrics breakdown accurate lifetime assessment methodology
-
G. Ribes, S. Bruyere, M. Denais, F. Monsieur, D. Roy, E. Vincent, and Ghibaudo, "High-k dielectrics breakdown accurate lifetime assessment methodology," in IEEE International Reliability Physics Symposium Proceedings, 2005, pp. 61-66.
-
(2005)
IEEE International Reliability Physics Symposium Proceedings
, pp. 61-66
-
-
Ribes, G.1
Bruyere, S.2
Denais, M.3
Monsieur, F.4
Roy, D.5
Vincent, E.6
-
25
-
-
20444441991
-
Review on high-k dielectrics reliability issues
-
G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on high-k dielectrics reliability issues," IEEE Transactions on Device and Materials Reliability, Vol. 5, pp. 5-19, 2005.
-
(2005)
IEEE Transactions on Device and Materials Reliability
, vol.5
, pp. 5-19
-
-
Ribes, G.1
Mitard, J.2
Denais, M.3
Bruyere, S.4
Monsieur, F.5
Parthasarathy, C.6
Vincent, E.7
Ghibaudo, G.8
-
26
-
-
23844451438
-
Hot carrier degradation of HfSiON gate dielectrics with TiN electrode
-
J. H. Sim, B. H. Lee, R. Choi, S. C. Song, and G. Bersuker, "Hot carrier degradation of HfSiON gate dielectrics with TiN electrode," IEEE Transactions on Device and Materials Reliability, Vol. 5, pp. 177-182, 2005.
-
(2005)
IEEE Transactions on Device and Materials Reliability
, vol.5
, pp. 177-182
-
-
Sim, J.H.1
Lee, B.H.2
Choi, R.3
Song, S.C.4
Bersuker, G.5
-
27
-
-
20644440412
-
Threshold voltage instabilities in high-? gate dielectric stacks
-
S. Zafar, A. Kumar, E. Gusev, and E. Cartier, "Threshold voltage instabilities in high-? gate dielectric stacks," IEEE Transactions on Device and Materials Reliability, Vol. 5, pp. 45-64, 2005.
-
(2005)
IEEE Transactions on Device and Materials Reliability
, vol.5
, pp. 45-64
-
-
Zafar, S.1
Kumar, A.2
Gusev, E.3
Cartier, E.4
-
28
-
-
46049085849
-
An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks
-
A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Y. Kang, B. H. Lee, and R. Jammy, "An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks," in Technical Digest - International Electron Devices Meeting, IEDM, 2006.
-
(2006)
Technical Digest - International Electron Devices Meeting, IEDM
-
-
Neugroschel, A.1
Bersuker, G.2
Choi, R.3
Cochrane, C.4
Lenahan, P.5
Heh, D.6
Young, C.7
Kang, C.Y.8
Lee, B.H.9
Jammy, R.10
-
29
-
-
34250785121
-
Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors
-
G. Bersuker, J. H. Sim, C. S. Park, C. D. Young, S. Nadkarni, R. Choi, and B. H. Lee, "Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors," Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International, pp. 179-183, 2006.
-
(2006)
Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International
, pp. 179-183
-
-
Bersuker, G.1
Sim, J.H.2
Park, C.S.3
Young, C.D.4
Nadkarni, S.5
Choi, R.6
Lee, B.H.7
-
30
-
-
0032097793
-
Modeled tunnel currents for high dielectric constant dielectrics
-
E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Henson, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. J. Wortman, "Modeled tunnel currents for high dielectric constant dielectrics," IEEE Transactions on Electron Devices, Vol. 45, pp. 1350-1355, 1998.
-
(1998)
IEEE Transactions on Electron Devices
, vol.45
, pp. 1350-1355
-
-
Vogel, E.M.1
Ahmed, K.Z.2
Hornung, B.3
Henson, W.K.4
McLarty, P.K.5
Lucovsky, G.6
Hauser, J.R.7
Wortman, J.J.8
-
31
-
-
51549091027
-
Performance and reliability characteristics of the band edge high-k/metal gate nMOSFETs with La-doped Hf-silicate gate dielectrics
-
C. Y. Kang, C. S. Park, D. Heh, C. Young, P. Kirsch, H. B. Park, R. Choi, G. Bersuker, J. W. Yang, B. H. Lee, J. Lichtenwalner, J. S. Jur, A. I. Kingon, and R. Jammy, "Performance and reliability characteristics of the band edge high-k/metal gate nMOSFETs with La-doped Hf-silicate gate dielectrics," in IEEE International Reliability Physics Symposium Proceedings, 2008, pp. 663-664.
-
(2008)
IEEE International Reliability Physics Symposium Proceedings
, pp. 663-664
-
-
Kang, C.Y.1
Park, C.S.2
Heh, D.3
Young, C.4
Kirsch, P.5
Park, H.B.6
Choi, R.7
Bersuker, G.8
Yang, J.W.9
Lee, B.H.10
Lichtenwalner, J.11
Jur, J.S.12
Kingon, A.I.13
Jammy, R.14
-
32
-
-
64549091848
-
The Impact of La-doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs under Various Gate Stress Conditions
-
C. Y. Kang, C. D. Young, J. Huang, P. Kirsch, D. Heh, P. Sivasubramani, H. K. Park, B. G. B. H. Lee, H.S. Choi, K.T. Lee, Y-H. Jeong, J. Lichtenwalner, A. I. Kingon, H-H Tseng, and R. Jammy, "The Impact of La-doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs under Various Gate Stress Conditions," in Technical Digest - International Electron Devices Meeting, 2008, pp. p.115-118.
-
(2008)
Technical Digest - International Electron Devices Meeting
, pp. 115-118
-
-
Kang, C.Y.1
Young, C.D.2
Huang, J.3
Kirsch, P.4
Heh, D.5
Sivasubramani, P.6
Park, H.K.7
Lee, B.G.B.H.8
Choi, H.S.9
Lee, K.T.10
Jeong, Y.-H.11
Lichtenwalner, J.12
Kingon, A.I.13
Tseng, H.-H.14
Jammy, R.15
|