Intrinsic threshold voltage instability of the HFO2 NMOS transistors

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2006, Pages 179-183

  Bersuker, G ^a   Sim, J H ^a   Park, C S ^a   Young, C D ^a   Nadkarni, S ^a   Choi, R ^a   Lee, B H ^b  

^a SEMATECH   (United States)

^b IBM   (United States)

Author keywords

Electron traps; High k; Threshold voltage instability

Indexed keywords

PRE-EXISTING DEFECTS; THRESHOLD VOLTAGE INSTABILITY;

ELECTRON TRAPS; GATE DIELECTRICS; LOW TEMPERATURE OPERATIONS; MOS DEVICES; THRESHOLD VOLTAGE;

TRANSISTORS;

EID: 34250785121     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2006.251213     Document Type: Conference Paper

References (9)

1. G. Bersuker et al., Materials Today, p.26, Jan, 2004
2. J. H. Sim et al., SSDM, 214 (2004)
3. B. H. Lee et al., IEDM Tech. Dig., 859 (2004)
4. C. Young et al., IRPS Proc.,75, 2005
5. G. Bersuker et al., APL, 87, 042905 (2005)
6. G. Bersuker et al., Microel. Reliability, 44, 1509 (2004)
7. G. Ribes et al., IEEE-IRW, 2005
8. G. Bersuker et al., Proc. NATO Workshop on Defects in High-k Materials, St. Petersburg, July 2005
9. J. Gavartin et al., to be published