Impact of metal gate work function on nano CMOS device performance

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn 1, Issue , 2004, Pages 57-60

  Hou, Y T ^a,b   Low, Tony ^a   Xu, Bin ^a   Li, Ming Fu ^a,b   Samudra, G ^a   Kwong, D L ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS SCALING; GATE WORK FUNCTION; HIGH-K DIELECTRICS; ULTRA-THIN BODY;

COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; ELECTRONIC STRUCTURE; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 21644439155     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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