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Volumn 24, Issue 10, 2009, Pages

Investigations on the physical limitation and electrostatic improvement of a gate-all-around silicon nanowire transistor with Schottky barrier source/drain

Author keywords

[No Author keywords available]

Indexed keywords

DEPINNING; DOPANT SEGREGATION; DRAIN-INDUCED BARRIER LOWERING; ELECTROSTATIC PROPERTIES; GATE-ALL-AROUND; NONUNIFORM; OPTIMIZED CONDITIONS; PHYSICAL LIMITATIONS; QUANTITATIVE ASSESSMENTS; SCHOTTKY BARRIER HEIGHTS; SCHOTTKY BARRIERS; SILICON NANOWIRE TRANSISTORS; SUBTHRESHOLD; SUBTHRESHOLD SWING;

EID: 70350641407     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/24/10/105001     Document Type: Article
Times cited : (9)

References (39)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.