Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 54-55

  Kobayashi, Masaharu ^a   Kinoshita, Atsuhiro ^a   Saraswat, Krishna ^a   Wong, H S Philip ^a   Nishi, Yoshio ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; FERMIONS; GERMANIUM; METALS; MODULATION; SEMICONDUCTOR METAL BOUNDARIES; TECHNOLOGY;

DEPINNING; FERMI-LEVEL PINNING; N-MOSFET; SCHOTTKY BARRIER HEIGHT MODULATION; SCHOTTKY JUNCTIONS; SCHOTTKY-BARRIER HEIGHT; SOURCE/DRAIN RESISTANCE; VLSI TECHNOLOGIES;

SCHOTTKY BARRIER DIODES;

EID: 51949085061     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588561     Document Type: Conference Paper

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