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0028481246
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Improved array architectures of DINOR for 0.5 μm 32 M and 64 Mbit flash memories
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H. Onoda, Y. Kunori, K. Yuzuriha, S. Kobayashi, K. Sakakibara, M. Ohi, A. Fukumoto, N. Ajika, M. Hatanaka, and H. Miyoshi, "Improved array architectures of DINOR for 0.5 μm 32 M and 64 Mbit flash memories," IEICE Trans. Electron., vol. E77-C, no. 8, pp. 1279-1286, 1994.
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0029255454
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A 3.3 V-only 16 Mb DINOR flash memory
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S. Kobayashi, M. Mihara, Y. Miyawaki, M. Ishii, T. Futatsuya, A. Hosogane, A. Ohba, Y. Terada, N. Ajika, Y. Kunori, K. Yuzuriha, M. Hatanaka, H. Miyoshi, T. Yoshihara, Y. Uji, A. Matsuo, Y. Taniguchi, and Y. Kiguchi, "A 3.3 V-only 16 Mb DINOR flash memory," in ISSCC Dig. Tech. Papers, 1995, pp. 122-123.
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0029197224
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Effects of erase source bias on flash EPROM device reliability
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Novel electron injection method using band-to-band tunneling induced hot electron (BBHE) for flash memory with a P-channel cell
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T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka, and H. Miyoshi, "Novel electron injection method using band-to-band tunneling induced hot electron (BBHE) for flash memory with a P-channel cell," in IEDM Tech. Dig., 1995, pp. 279-282.
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0029723468
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A high programming throughput 0.35 μm P-channel DINOR flash memory
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O. Sakamoto, H. Onoda, T. Katayama, K. Hayashi, N. Yamasaki, K. Sakakibara, T. Ohnakado, H. Takada, N. Tsuji, N. Ajika, M. Hatanaka, and H. Miyoshi, "A high programming throughput 0.35 μm P-channel DINOR flash memory," in Symp. VLSI Tech., 1996, pp. 222-223.
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The impact of gate-induced drain leakage current on MOSFET scaling
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A high speed, low power P-channel flash EEPROM using silicon rich oxide as tunneling dielectric
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C. C.-H. Hsu, A. Acovic, L. Dori, B. Wu, T. Lii, D. Quinlan, D. DiMaria, Y. Taur, M. Wordeman, and T. Ning, "A high speed, low power P-channel flash EEPROM using silicon rich oxide as tunneling dielectric," Ext. Abstr. SSDM, 1992, pp. 140-142.
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A flash-erase EEPROM cell with an asymmetric source and drain structure
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H. Kume, H. Yamamoto, T. Adachi, T. Hagiwara, K. Komori, T. Nishimoto, A. Koike, S. Meguro, T. Hayashida, and T. Tsukada, "A flash-erase EEPROM cell with an asymmetric source and drain structure," in IEDM Tech. Dig., 1987, pp. 560-563.
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Degradation mechanism of flash EEPROM programming after program/erase cycles
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S. Yamada, Y. Hiura, T. Yamane, K. Amemiya, Y. Ohsima, and K. Yoshikawa, "Degradation mechanism of flash EEPROM programming after program/erase cycles," in IEDM Tech. Dig., 1993, pp. 23-26.
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0028737004
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Flash EPROM endurance simulation using physics-based models
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J. Z. Peng, S. Haddad, H. Fang, C. Chang, S. Longcor, B. Ho, Y. Sun, D. Liu, Y. Tang, J. Hsu, S. Luan, and J. Lien, "Flash EPROM endurance simulation using physics-based models," in IEDM Tech. Dig., 1994, pp. 295-298.
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