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Volumn 19, Issue 7, 1998, Pages 253-255

A new SONOS memory using source-side injection for programming

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; EFFICIENCY; ELECTRON TUNNELING; NITRIDES; OXIDES; SEMICONDUCTING SILICON;

EID: 0032123105     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.701434     Document Type: Article
Times cited : (54)

References (10)
  • 1
    • 0029512456 scopus 로고
    • High endurance ultrathin tunnel oxide for dynamic memory application
    • C. Wann and C. Hu, "High endurance ultrathin tunnel oxide for dynamic memory application," in IEDM Tech. Dig., 1995, pp. 867-870.
    • (1995) IEDM Tech. Dig. , pp. 867-870
    • Wann, C.1    Hu, C.2
  • 2
    • 0029409435 scopus 로고
    • High endurance ultrathin tunnel oxide in MONOS device structure for dynamic memory application
    • _, "High endurance ultrathin tunnel oxide in MONOS device structure for dynamic memory application," IEEE Electron Device Lett., vol. 16, pp. 491-493, 1995.
    • (1995) IEEE Electron Device Lett. , vol.16 , pp. 491-493
  • 3
    • 0020708742 scopus 로고
    • A low-voltage alterable EEPROM with metal-oxide-nitride-oxide-semiconductor (MONOS) structures
    • Feb.
    • E. Suzuki, H. Hiraishi, K. Ishii, and Y. Hayashi, "A low-voltage alterable EEPROM with metal-oxide-nitride-oxide-semiconductor (MONOS) structures," IEEE Trans. Electron Devices, vol. ED-30, pp. 122-128, Feb. 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , pp. 122-128
    • Suzuki, E.1    Hiraishi, H.2    Ishii, K.3    Hayashi, Y.4
  • 5
    • 0024985779 scopus 로고
    • Charge transport and storage of low programming voltage SONOS/MONOS memory devices
    • F. R. Libsch and M. H. White, "Charge transport and storage of low programming voltage SONOS/MONOS memory devices," Solid State Electron., vol. 33, no. 1, pp. 105-126, 1990.
    • (1990) Solid State Electron. , vol.33 , Issue.1 , pp. 105-126
    • Libsch, F.R.1    White, M.H.2
  • 7
    • 0022985546 scopus 로고
    • A novel high-speed 5-volt programming EPROM structure with source-side injection
    • A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, "A novel high-speed 5-volt programming EPROM structure with source-side injection," in IEDM Tech. Dig., 1986, pp. 584-587.
    • (1986) IEDM Tech. Dig. , pp. 584-587
    • Wu, A.T.1    Chan, T.Y.2    Ko, P.K.3    Hu, C.4
  • 8
    • 0024870476 scopus 로고
    • A new flash-erase EEPROM cell with a sidewall select-gate on its source-side
    • K. Naruka, S. Yamada, E. Obi, S. Taguchi, and M. Wads, "A new flash-erase EEPROM cell with a sidewall select-gate on its source-side," in IEDM Tech. Dig., 1989, pp. 603-606.
    • (1989) IEDM Tech. Dig. , pp. 603-606
    • Naruka, K.1    Yamada, S.2    Obi, E.3    Taguchi, S.4    Wads, M.5
  • 9
    • 0028602570 scopus 로고
    • A novel high density contactless flash memory array using split-gate source-side injection cell for 5 V-only applications
    • Y. Ma, C. Pang, J. Pathak, S. Tsao, C. Chang, Y. Yamauchi, and M. Yoshimi, "A novel high density contactless flash memory array using split-gate source-side injection cell for 5 V-only applications," in Symp. VLSI Technol., 1994, p. 49.
    • (1994) Symp. VLSI Technol. , pp. 49
    • Ma, Y.1    Pang, C.2    Pathak, J.3    Tsao, S.4    Chang, C.5    Yamauchi, Y.6    Yoshimi, M.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.