Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

IET Computers and Digital Techniques

Volumn 3, Issue 3, 2009, Pages 289-303

  Fazeli, M ^a   Miremadi, S G ^a   Ejlali, A ^a   Patooghy, A ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUB MICRON TECHNOLOGIES; DELAY ELEMENTS; FEATURE SIZES; FEEDBACK LINES; FILTER SETS; LOW ENERGIES; SEU TOLERANCES; SINGLE EVENT UPSETS; SINGLE EVENTS; SINGLE-EVENT TRANSIENTS; SPICE SIMULATIONS; TRIPLE MODULAR REDUNDANCIES;

DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; JITTER;

TRANSIENTS;

EID: 64549144240     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0099     Document Type: Article

References (49)

1. Vijaykrishnan, N., and Xie, Y.: ' Reliability concerns in embedded system designs ', IEEE Comput., 2006, 39, (1), p. 118-120
2. Mitra, S., Karnik, T., Seifert, N., and Zhang, M.: ' Logic soft errors in sub-65nm technologies design and CAD challenges ', Proc. Design Automation Conference (DAC), Anaheim, CA, June, 2005, p. 2-4
3. Hazucha, P., and Svensson, C.: ' Impact of CMOS technology scaling on the atmospheric neutron soft error rate ', IEEE Trans. Nucl. Sci., 2000, 47, (6), p. 2586-2594 10.1109/23.903813 0018-9499
4. Mitra, S., Seifert, N., Zhang, M., Shi, Q., and Kim, K.S.: ' Robust system design with built-in soft-error resilience ', IEEE Comput., 2005, 38, (2), p. 43-52
5. Hass, K., and Gambles, J.: ' Single event transients in deep submicron CMOS ', Proc. Midwest Symposium on Circuits and Systems, 1999, p. 122-125
6. Mitra, S., Zhang, M., Mak, T.M., Seifert, N., Zia, V., and Kim, K.S.: ' Logic soft errors: a major barrier to robust platform design ', Proc. Int. Test Conference, November, 2005, p. 687-696
7. Seifert, N., Shipleg, P., Pant, M.D., Ambrose, V., and Gil, B.: ' Radiation induced clock jitter and race ', Int. Physics Reliability Symposium, San Jose, CA, April, 2005, IRPS, p. 215-222
8. Cohen, N., Sriram, T.S., Leland, N., Moyer, D., Butler, S., and Flatley, R.: ' Soft error considerations for deep-submicron CMOS circuit applications ', Int. Electron Devices Meeting, Washington, DC, 1999, p. 315-318
9. Keyes, R.W.: ' Fundamental limits of silicon technology ', Proc. IEEE, 2001, 89, (3), p. 227-339 10.1109/5.915372 0018-9219
10. Zhou, K., and Mohanram, K.: ' Gate sizing to radiation harden combinational logic ', IEEE Trans. CAD, 2006, 25, (1), p. 155-166 0278-0070
11. Seifert, N., Slankard, P., and Kirsch, M.: et al. ' Radiation-induced soft error rates of advanced CMOS bulk devices ', Proc. IEEE Int. Physics Symposium, 2006, p. 217-225
12. Kastensmidt, F., Sterpone, L., Sonza Reorda, M., and Carro, L.: ' On the optimal design of triple modular redundancy logic for SRAM-based FPGAs ', Proc. IEEE Design, Automation and Test in Europe, 2005, p. 1290-1295
13. Favalli, M., and Metra, C.: ' TMR voting in the presence of crosstalk faults at the voter inputs ', IEEE Trans. Reliab., 2004, 53, (3), p. 342-348 10.1109/TR.2004.833308 0018-9529
14. Sterpone, L., and Violante, M.: ' Analysis of the robustness of the TMR architecture in SRAM-based FPGAs ', IEEE Trans. Nucl. Sci., 2005, 52, (5), p. 1545-1549 10.1109/TNS.2005.856543 0018-9499
15. Stachetti, V., Gaisler, J., Goller, G., and Gargasson, C.L.: ' 32-BIT processing unit for embedded space flight applications ', IEEE Trans. Nucl. Sci., 1996, 43, (3), p. 873-878 10.1109/23.510727 0018-9499
16. Gaisler, J.: ' A portable and fault-tolerant microprocessor based on the SPARC V8 architecture ', Proc. IEEE/IFIP Int. Conf. Dependable Systems and Networks, June, 2002, p. 409-415
17. Maheshwari, A., Burleson, W., and Tessier, R.: ' Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits ', IEEE Trans. VLSI, 2004, 12, (3), p. 299-311 1063-8210
18. Whitaker, S.R., Canaris, J., and Liu, K.: ' SEU hardened memory cells for CCSDS reed Solomon encoder ', IEEE Trans. Nucl. Sci., 1991, 38, (6), p. 1471-1477 10.1109/23.124134 0018-9499
19. Zhao, Y., and Dey, S.: ' Separate dual-transistor registers - a circuit solution for on-line testing of transient error in UDSM-IC ', Proc. 9th IEEE Int. On-Line Testing Symposium, 2003, p. 7-11
20. Monnier, T., Roche, F.M., and Cathebras, G.: ' Flip-flop hardening for space applications ', Proc. IEEE Workshop on Memory Technology, Design and Testing, 1998, p. 104-107
21. Wang, L., Yue, S., and Zhao, Y.: ' Low-overhead SEU-tolerant latches ', Proc. Int. Conf. Microwave and Millimeter Wave Technology, China, April, 2007, p. 1-4
22. Omana, M., Rossi, D., and Metra, C.: ' Latch susceptibility to transient faults and new hardening approach ', IEEE Trans. Comput., 2007, 56, (9), p. 1255-1268 0018-9340
23. Zhu, D., Melhem, R., and Mosse, D.: ' The effects of energy management on reliability in real-time embedded systems ', Proc. Int. Conf. CAD, 2004, p. 35-40
24. Seifert, N., Moyer, D., Leland, N., and Hokinson, R.: ' Historical trend in alpha-particle induced soft error rates of the alpha microprocessor ', Proc. 39th IEEE Int. Reliability Physics Symposium, 2001, p. 259-265
25. Fazeli, M., Patooghy, A., Miremadi, S.G., and Ejlali, A.: ' Feedback redundancy: a power-aware SEU-tolerant latch design in DSM technologies ', Proc. IEEE/IFIP Int. Conf. Dependable Systems and Networks, Edinburg, UK, June, 2007, p. 276-285
26. Mitra, S., Zhang, M., Waqas, S., Seifert, N., Gill, B., and Kim, K.S.: ' Combinational logic soft error correction ', Proc. IEEE Int. Test Conference, Santa Clara, California, USA, November, 2006, p. 1-9
27. Zhang, M., and Shanbhag, N.: ' A transient-tolerant high-performance circuit style ', Proc. IEEE Workshop on System Effects of Logic Soft Errors, Urbana Champaign, Illinois, April, 2006
28. Mitra, S., Zhang, M., Seifert, N., Mak, T.M., and Kee, S.K.: ' Soft error resilient system design through error correction ', Proc. IFIP Int. Conf. Very Large Scale Integration, October, 2006, p. 332-337
29. Wang, W., and Gong, H.: ' Edge triggered pulse latch design with delayed latching edge for radiation hardened application ', IEEE Trans. Nucl. Sci., 2004, 51, (6), p. 3626-3630 10.1109/TNS.2004.839154 0018-9499
30. Nicolaidis, M.: ' Design for soft error mitigation ', IEEE Trans. Device Mater. Reliab., 2005, 5, (3), p. 405-418 10.1109/TDMR.2005.855790 1530-4388
31. Anghel, L., Alexandrescu, D., and Nicolaidis, M.: ' Evaluation of a soft error tolerance technique based on time and/or space redundancy ', Proc. 13th Symposium on Integrated Circuits and Systems Design, Manaus, Brazil, September, 2000, p. 237-242
32. Krishnamohan, S., and Mahapatra, N.R.: ' A highly-efficient technique for reducing soft errors in static CMOS circuits ', Proc. IEEE Int. Conf. Computer Design, San Jose, California, October, 2004, p. 126-13
33. Gadlage, M.J., Schrimpf, R.D., and Benedetto, J.M.: et al. ' Single event transient pulse widths in digital microcircuits ', IEEE Trans. Nucl. Sci., 2004, 51, (6), p. 3285-3290 10.1109/TNS.2004.839174 0018-9499
34. Benedetto, J.M., Eaton, P.H., Mavis, D.G., Gadlage, M., and Turflinger, T.: ' Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes ', IEEE Trans. Nucl. Sci., 2005, 52, (6), p. 2114-2119 10.1109/TNS.2005.860679 0018-9499
35. Kohler, R.A., and Koga, R.: ' SEU characterization of hardened CMOS SRAMS using statistical analysis of feedback delay in memory cells ', IEEE Trans. Nucl. Sci., 1989, 36, (6), p. 2318-2323 10.1109/23.45442 0018-9499
36. Karnik, T., Hazucha, P., and Patel, J.: ' Characterization of soft errors caused by single event upsets in CMOS processes ', IEEE Trans. Dependable Secur. Comput., 2004, 1, (2), p. 128-143 10.1109/TDSC.2004.14 1545-5971
37. Gyudong, K., Min-Kyu, K., Byoung-Soo, C., and Wonchan, K.: ' A low-voltage, low-power CMOS delay element ', IEEE J. Solid-State Circuits, 1996, 31, (7), p. 966-971 10.1109/4.508210 0018-9200
38. Mahapatra, N.R., Tareen, A., and Garimella, S.V.: ' Comparison and analysis of delay elements ', Proc. 45th Midwest Symposium on Circuits and Systems, August, 2002, p. 473-476
39. Ejlali, A., Al-Hashimi, B.M., Schmitz, M.T., Rosinger, P., and Miremadi, S.G.: ' Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems ', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2006, 14, (4), p. 323-335 1063-8210
40. Freeman, L.B.: ' Critical charge calculations for bipolar SRAM array ', J. Res. Dev., 1996, 40, (1), p. 119-129
41. Walstra, S.V., and Dai, C.: ' Circuit-level modeling of soft errors in integrated circuits ', IEEE Trans. Device Mater. Reliab., 2005, 5, (3), p. 358-364 1530-4388
42. Hazucha, P., Svensson, C., and Wender, S.: ' Cosmic-ray soft error rate characterization of a standard 0.6-m CMOS process ', IEEE J. Solid-State Circuits, 2000, 35, (10), p. 1422-1429 0018-9200
43. Singh, M., Rachala, R., and Koren, I.: ' Transient fault sensitivity analysis of analog-to-digital converters (ADC's) ', Proc. IEEE Annual Workshop on VLSI, April, 2001, p. 140-145
44. Zhao, W., and Cao, Y.: ' New generation of predictive technology model for sub-45nm early design exploration ', IEEE Trans. Electron Devices, 2006, 53, (11), p. 2816-2823 0018-9383
45. Cao, Y., Sato, T., Sylvester, D., Orshansky, M., and Hu, C.: ' New paradigm of predictive MOSFET and interconnect modeling for early circuit design ', Proc. IEEE Custom Integrated Circuits Conference, Orlando, FL, May, 2000, p. 201-204
46. Hazucha, P., Karnik, T., and Walstra, S.: et al. ' Measurements and analysis of SER tolerant latch in a 90-nm dual-Vt CMOS process ', IEEE Custom Integrated Circuits Conference, 2003, p. 617-620
47. Pedram, M., and Rabaey, J.: ' Power aware design methodologies ', (Kluwer, Norwell, MA, 2002)
48. Seifert, N., and Tam, N.: ' Timing vulnerability factors of sequentials ', IEEE Trans. Device Mater. Reliab., 2004, 4, (3) 1530-4388
49. Calin, T., Nicolaidis, M., and Velazco, R.: ' Upset hardened memory design for submicron CMOS technology ', IEEE Trans. Nucl. Sci., 1996, 43, (6), p. 2874-2878 0018-9499