Evaluation of a soft error tolerance technique based on time and/or space redundancy

Proceedings - 13th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2000, Pages 237-242

  Anghel, L ^a   Alexandrescu, D ^a   Nicolaidis, M ^a  

^a TIMA LABORATORY   (France)

Author keywords

Arithmetic; Circuit simulation; Circuit testing; Discrete event simulation; Fault tolerance; Integrated circuit noise; Manufacturing; Power supplies; Redundancy; Silicon

Indexed keywords

DIGITAL ARITHMETIC; DISCRETE EVENT SIMULATION; ERROR CORRECTION; ERRORS; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; LOGIC CIRCUITS; MANUFACTURE; MICROPROCESSOR CHIPS; RADIATION HARDENING; REDUNDANCY; SILICON; SYSTEMS ANALYSIS;

CIRCUIT TESTING; EVENT-DRIVEN SIMULATORS; FAULT TOLERANCE TECHNIQUES; FAULT TOLERANT TECHNIQUE; INTEGRATED CIRCUIT NOISE; MANUFACTURING TESTING; POWER SUPPLY; SOFT-ERROR TOLERANCE;

CIRCUIT SIMULATION;

EID: 84944215733     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2000.876036     Document Type: Conference Paper

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