A highly-efficient technique for reducing soft errors in static CMOS circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 126-131

  Krishnamohan, Srivathsan ^a   Mahapatra, Nihar R ^a  

^a Michigan State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; RELIABILITY; SPURIOUS SIGNAL NOISE;

DESIGN ROBUSTNESS; ERROR MASKING; LATCHING-WINDOW MASKED; SOFT ERRORS;

CMOS INTEGRATED CIRCUITS;

EID: 17644410453     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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