Soft error resilient system design through error correction

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 332-337

  Mitra, Subhasish ^a   Zhang, Ming ^b   Seifert, Norbert ^b   Mak, T M ^b   Kim, Kee Sup ^b  

^a STANFORD UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT IN SOFT ERROR RESILIENCE; CHIP LEVEL POWER; COMBINATIONAL LOGICS; DESIGN TRADE-OFFS; ERROR-DETECTION TECHNIQUES; IN-CHIP; INTERNATIONAL CONFERENCES; MINIMAL AREA; ORDER-OF MAGNITUDES; PERFORMANCE IMPACTS; RECOVERY MECHANISMS; SOFT ERROR PROTECTION; SOFT ERRORS; SOFT ERRORS (SE); SYSTEM DESIGNS; SYSTEM ON CHIP (SOCS); VERY LARGE SCALE INTEGRATION (VLSI);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ERROR DETECTION; FUZZY LOGIC; INTEGRATED CIRCUITS; LSI CIRCUITS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; VIDEO STREAMING;

ERROR CORRECTION;

EID: 46249126050     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313256     Document Type: Conference Paper

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