Comparison and analysis of delay elements

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Mahapatra, Nihar R ^a   Tareen, Alwin ^a   Garimella, Sriram V ^a,b  

^a UNIVERSITY AT BUFFALO   (United States)

^b Andiamo Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; SIGNAL PROCESSING; VLSI CIRCUITS; VOLTAGE CONTROL;

SIGNAL INTEGRITY;

DELAY CIRCUITS;

EID: 0036976596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. G. Kim, M.-K. Kim, B.-S. Chang, and W. Kim, "A low-voltage, low-power CMOS delay element," IEEE Journal of Solid State Circuits, Vol. 31, No. 7, pp. 966-971, Jul. 1996.
2. J.M. Rabaey, "Digital integrated circuits: A design perspective," Prentice-Hall Book Company, 1st edition, ISBN #0-13-178609-1, Upper Saddle River, NJ, 1996.
3. Yuk-Wah Pang, Wing-yun Sit, Chiu-sing Choy, Cheong-fat Chan and Wai-kuen Cham, "An asynchronous cell library for self-timed system designs," IEICE Transactions on Information and Systems, Vol. E80-D, No. 3, pp. 296-305, Mar. 1997.
4. M.F. Aburdene, J. Zheng and R.J. Kozick, "New recursive VLSI architectures for forward and inverse discrete cosine transform,"Proceedings of SPIE - The International Society for Optical Engineering, Vol. 2669, pp. 59-65, 1996.
5. N.R. Mahapatra, S.V. Garimella, and A. Tareen, "Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation," Proc. 2000 IEEE International Symposium on Circuits and Systems, Vol. II, pp. 537-540, Geneva, Switzerland, May 28-31, 2000.