Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 10, 2000, Pages 1422-1429

  Hazucha, Peter ^a   Svensson, Christer ^a   Wender, Stephen A ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b LOS ALAMOS NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; ELECTRIC CHARGE; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RANDOM ACCESS STORAGE; RELIABILITY;

COSMIC RAY SOFT ERROR RATE; NOISE CURRENT; SINGLE EVENT SET UP; STATIC MEMORY CELL;

CMOS INTEGRATED CIRCUITS;

EID: 0034297471     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.871318     Document Type: Article

References (18)

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