Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

IEEE Transactions on Nuclear Science

Volumn 52, Issue 5 II, 2005, Pages 1545-1549

  Sterpone, L ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

RADIATION HARDENING; STATIC RANDOM ACCESS STORAGE;

SINGLE EVENT UPSETS (SEU); TRIPLE MODULE REDUNDANCY;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 29144456645     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.856543     Document Type: Conference Paper

References (15)

1. E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa, and A. Salazar, "Radiation test results of the virtex FPGA and ZBT SRAM for space based reconfigurable computing," presented at the MAPLD, Sep. 1999.
2. M. Ceschia, A. Paccagnella, S.-C. Lee, C. Wan, M. Bellato, M. Menichelli, A. Papi, A. Kaminski, and J. Wyss, "Ion beam testing of ALTERA APEX FPGA's," presented at the NSREC Radiation Effects Data Workshop Record, Phoenix, AZ, Jul. 2002.
3. Triple Module Redundancy Design Techniques for Virtex FPGAs, 2001.
4. E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, and J. Fabula, "Radiation testing update, SEU mitigation, and availability analysis of the virtex FPGA for space re-configurable computing," presented at the IEEE Nuclear and Space Radiation Effects Conf., Jul. 2000.
5. M. Bellato, M. Ceschia, M. Menichelli, A. Papi, J. Wyss, and A. Paccagnella, "Ion beam testing of SRAM-based FPGA's," presented at the IEEE Radiation Effects Data Workshop, Jul. 2002.
6. M. Alderighi, F. Casini, S. D'Angelo, F. Faure, M. Mancini, S. Pastore, G. R. Sechi, and R. Velazco, "Radiation test methodology for SRAM-based FPGA's by using THESIC+," in Proc. IEEE On-Line Testing Symp., 2003, p. 162.
7. M. Ceschia, M. Violante, M. S. Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori, "Identification and classification of single event upsets in the configuration memory of SRAM based FPGAs," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2088-2094, Dec. 2003.
8. M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Cerchia, A. Paccagnella, M. Rebaudengo, M. S. Reorda, M. Violante, and P. Zambolin, "Evaluating the effects of SEU's affecting the configuration memory of an SRAM-based FPGAs," presented at the IEEE Design Automation and Test in Europe, 2004.
9. F. Lima, C. Carmichael, J. Fabula, R. Padovani, and R. Reis, "A fault injection analysis of virtex FPGA TMR methodology," in Proc. IEEE Eur. Conf. Radiation and Its Effect on Component and Systems, 2001, pp. 275-282.
10. M. Alderighi, S. D'Angelo, M. Mancini, and G. R. Sechi, "A fault injection tool for SRAM-based FPGAs," in Proc. IEEE On-Line Testing Symp., 2003, pp. 129-133.
11. M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, A. Marmo, S. Pastore, and G. R. Sechi, "A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx virtex FPGAs," in Proc. IEEE Symp. Defect and Fault Tolerance in VLSI System, 2003, pp. 71-78.
12. Correcting Single-Event Upsets Through Virtex Partial Reconfiguration, 2000.
13. F. Lima, L. Cairo, and R. Reis, "Designino fault tolerant systems into SRAM-based FPGAs," in Proc. ACM/IEEE Design Automation Conf., 2003, pp. 650-655.
14. M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. S. Reorda, and A. Paccagnella, "Simulation-based analysis of SEU effects in SRAM-based FPGAs," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3354-3359, Dec. 2004.
15. Spartan-II 2.5 V FPGA Family: Introduction and Ordering Information, 2003.