Gate sizing to radiation harden combinational logic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 1, 2006, Pages 155-166

  Zhou, Quming ^a   Mohanram, K ^a  

^a Rice University   (United States)

Author keywords

70 to 180 nm; Combinational logic circuits; Gate level radiation hardening; Gate sizing; Logical masking probability; Single event upsets; Soft error failure rate

Indexed keywords

BOOLEAN ALGEBRA; COMPUTER AIDED LOGIC DESIGN; COST EFFECTIVENESS; COSTS; LOGIC GATES; PROBABILITY; RADIATION HARDENING;

70 TO 180 NM; COMBINATIONAL LOGIC CIRCUITS; GATE LEVEL RADIATION HARDENING; GATE SIZING; LOGICAL MASKING PROBABILITY; SINGLE EVENT UPSETS; SOFT ERROR FAILURE RATE;

GATES (TRANSISTOR);

EID: 31344449592     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.853696     Document Type: Article

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