Spice modeling of silicon nanowire field-effect transistors for high-speed analog integrated circuits

IEEE Transactions on Nanotechnology

Volumn 7, Issue 6, 2008, Pages 766-775

  Hamedi Hagh, Sotoudeh ^a   Bindal, Ahmet ^a  

^a SAN JOSE STATE UNIVERSITY   (United States)

Author keywords

Field effect transistor; High frequency; Modeling; Nanowire; Silicon

Indexed keywords

ANALOG CIRCUITS; CUTOFF FREQUENCY; DRAIN CURRENT; ELECTRIC RESISTANCE; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; NANOWIRES; SPICE; TRANSISTORS;

ANALOG INTEGRATED CIRCUITS; CHANNEL LENGTHS; CHANNEL RADIUSES; DISTRIBUTED DEVICES; FALL TIMES; FIELD-EFFECT TRANSISTOR; FULLY DEPLETED; GAIN CUTOFF FREQUENCIES; GATE CONTROLS; GHZ FREQUENCIES; HIGH FREQUENCY; INPUT SIGNALS; LOW POWERS; MAXIMUM FREQUENCY OF OSCILLATIONS; MODELING; OFF CURRENTS; OPERATING REGIONS; OUTPUT RESISTANCES; OUTPUT SWINGS; PARASITICS; RF APPLICATIONS; RISE TIMES; SHORT-CHANNEL EFFECTS; SIGNAL OPERATIONS; SILICON NANOWIRES; SURROUNDING GATE TRANSISTORS; SURROUNDING GATES; VERY-LARGE-SCALE INTEGRATIONS;

FIELD EFFECT TRANSISTORS;

EID: 58149218289     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2008.2004409     Document Type: Article

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