A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 241-244

  Su, Pin ^a   Fung, Samuel K H ^a   Wyatt, Peter W ^b   Wan, Hui ^a   Chan, Mansun ^a   Niknejad, Ali M ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MIT LINCOLN LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY;

CIRCUIT DESIGNS; CIRCUIT SIMULATORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242527294     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. P. Su, S. Fung, S. Tang, F. Assaderaghi and C. Hu, "BSIMPD: A partial-depletion SOI MOSFET model for deep-submicron CMOS designs," Proceedings of IEEE Custom IC Conference, 2000, pp. 197-200.
2. http://www-device.eecs.berkeley.edu/-bsimsoi
3. S. Fung et al., "A partially-depleted SOI compact model - formulation and parameter extraction," Tech. Digest of 2000 Symp. on VLSI Tech, p. 206.
4. J. Watts, "How to build an SOI compact model without violating the laws of physics," Tech. Proceedings of the 5th International Conf. on Modeling and Simulation of Microsystems NanoTech 2002 - MSM 2002, pp. 726-729.
5. H. Nakayama et al., "Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS," Proceedings of IEEE Custom IC Conference, 2001, pp. 381-384.
6. K. Goto, P. Su, Y. Tagawa, T. Sugii and C. Hu, "80nm SOI CMOS parameter extraction for BSIMPD," 2001 IEEE International SOI Conference Proceedings, pp. 55-56.
7. http://www.eigroup.org/cmc
8. P. Su et al., "On the body-source built-in potential lowering of SOI MOSFETs," IEEE Electron Device Letters, vol. 24, no. 2, February 2003.
9. P. Su, "An international standard model for SOI circuit design," Ph.D. dissertation, University of California at Berkeley, December 2002.
10. L. Su, J. Jacobs, J. Chung and D. Antoniadis, "Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's," IEEE Electron Device Letters, vol. 15, no. 9, pp. 366-369, September 1994.
11. Z. Liu et al., "Threshold voltage model for deep-submicrometer MOSFET's," IEEE Transactions On Electron Devices, vol. 40, no. 1, pp. 86-95, January 1993.