FinFET: The prospective multi-Gate device for future SoC applications

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn 2006-January, Issue , 2006, Pages 49-52

  Inaba, S ^b   Okano, K ^b   Izumida, T ^b   Kaneko, A ^a   Kawasaki, H ^b   Yagishita, A ^a   Kanemura, T ^b   Ishida, T ^b   Aoki, N ^b   Ishimaru, K ^b   Suguro, K ^a   Eguchi, K ^a   Tsunashima, Y ^a   Toyoshima, Y ^b   Ishiuchi, H ^b  

^a Manufacturing Engineering Center   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; LOW POWER ELECTRONICS; RECONFIGURABLE HARDWARE; SOLID STATE DEVICES; SUBSTRATES; SYSTEM-ON-CHIP;

BULK FINFET; COST EFFECTIVE; FLUCTUATION CONTROL; INTEGRATION SCHEME; MULTIGATE DEVICES; SELF ALIGNED DOUBLE GATES; SI SUBSTRATES; SOC APPLICATION;

INTEGRATED CIRCUITS;

EID: 34548535501     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307635     Document Type: Conference Paper

References (6)

1. D. Hisamoto, "Multi-gate FETs, " in IEDM short course, (2003) and the references in it.
2. K. Okano, et al., "Robust Device Design in FinFET SRAM for hp22 nm Technology Node, " in 2005 Silicon Nanoelectronics Workshop, pp. 14-15, Kyoto, (2005).
3. A. Kaneko, et al., "Sidewall Transfer Process and Selective Gate Sidewall Spacer Formation Technology for Sub-15nm FinFET with Elevated Source/Drain Extension, " in IEDM Tech. Dig., 34-6, pp. 863-866, Washington D.C., (2005).
4. T. Park, et al., "Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs), " in IEDM Tech. Dig., 2-2, pp. 27-30, Washington D.C., (2003).
5. K. Okano, et al., "Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length, " in IEDM Tech. Dig., 30-4, pp. 739-742, Washington D.C., (2005).
6. H. Kawasaki, et al., "Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond, " in 2006 Symp on VLSI Technology, 9.2, pp. 86-87, Honolulu, HI, (2006).