An exploratory design study of a 16 × 16 static random access memory using silicon nanowire transistors

Journal of Nanoelectronics and Optoelectronics

Volumn 2, Issue 3, 2007, Pages 294-303

  Bindal, Ahmet ^a   Hamedi Hagh, Sotoudeh ^a  

^a SAN JOSE STATE UNIVERSITY   (United States)

Author keywords

Low power design; Nanoelectronics; Nanotechnology; Nanowire transistors; Silicon nanowire transistors; SRAM

Indexed keywords

CHARGE COUPLED DEVICES; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; HEAT RADIATION; METALLIC COMPOUNDS; MOS DEVICES; NANOELECTRONICS; NANOTECHNOLOGY; NANOWIRES; RANDOM ACCESS STORAGE; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR MATERIALS; STATIC RANDOM ACCESS STORAGE; WORK FUNCTION;

ACCESS TIMES; CHANNEL TRANSISTORS; DESIGN CYCLES; DESIGN STUDIES; EFFECTIVE CHANNEL LENGTHS; LAYOUT AREAS; LAYOUT SIMULATIONS; LOW POWER DESIGN; MEMORY USING; METAL GATES; METAL WORK FUNCTIONS; NANOWIRE TRANSISTORS; ON CURRENTS; OPTIMAL DEVICE DIMENSIONS; POWER DISSIPATIONS; RANDOM ACCESSES; SEMICONDUCTOR TRANSISTORS; SILICON NANOWIRE TRANSISTORS; SRAM; STATIC AND DYNAMICS; TRANSIENT PERFORMANCES; WRITE OPERATIONS;

TRANSISTORS;

EID: 58049220111     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1166/jno.2007.309     Document Type: Article

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