-
1
-
-
0001114414
-
Silicon nanowire devices
-
0003-6951
-
Chung, S-W., Yu, J-Y., and Heath, J.R.: ' Silicon nanowire devices ', Appl. Phys. Lett., 2000, 76, (15), p. 2068-2070 0003-6951
-
(2000)
Appl. Phys. Lett.
, vol.76
, Issue.15
, pp. 2068-2070
-
-
Chung, S.-W.1
Yu, J.-Y.2
Heath, J.R.3
-
2
-
-
0000434281
-
Ti-catalyzed Si nanowires by chemical vapor deposition: Microscopy and growth mechanisms
-
0021-8979
-
Kamins, T.I., Williams, S.R., Basile, D.P., Hesjedal, T., and Harris, J.S.: ' Ti-catalyzed Si nanowires by chemical vapor deposition: microscopy and growth mechanisms ', J. Appl. Phys., 2001, 89, (2), p. 1008-1016 0021-8979
-
(2001)
J. Appl. Phys.
, vol.89
, Issue.2
, pp. 1008-1016
-
-
Kamins, T.I.1
Williams, S.R.2
Basile, D.P.3
Hesjedal, T.4
Harris, J.S.5
-
3
-
-
2642566816
-
Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces
-
0957-4484
-
Islam, M.S., Sharma, S., Kamins, T.I., and Williams, R.S.: ' Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces ', Nanotechnology, 2004, 15, p. L5-L8 0957-4484
-
(2004)
Nanotechnology
, vol.15
-
-
Islam, M.S.1
Sharma, S.2
Kamins, T.I.3
Williams, R.S.4
-
4
-
-
0037912948
-
Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction
-
Westwater, J., Gosain, D.P., Tomiya, S., Usui, S., and Ruda, H.: ' Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction ', J. Vac. Sci. Tech. B, 1997, 15, (3), p. 554-557
-
(1997)
J. Vac. Sci. Tech. B
, vol.15
, Issue.3
, pp. 554-557
-
-
Westwater, J.1
Gosain, D.P.2
Tomiya, S.3
Usui, S.4
Ruda, H.5
-
5
-
-
21644470779
-
A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM
-
Kikuchi, T., Moriya, S., Nakatsuka, Y., Matsuoka, H., Nakazato, K., Nishida, A., Chakihara, H., Matsuoka, M., and Moniwa, M.: ' A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM ', IEDM, 2004, p. 923-926
-
(2004)
IEDM
, pp. 923-926
-
-
Kikuchi, T.1
Moriya, S.2
Nakatsuka, Y.3
Matsuoka, H.4
Nakazato, K.5
Nishida, A.6
Chakihara, H.7
Matsuoka, M.8
Moniwa, M.9
-
6
-
-
28144432921
-
Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits
-
Ecoffey, S., Pott, V., Bouvet, D., Mazza, M., Mahapatra, S., Schmid, A., Leblebici, Y., Declercq, M.J., and Ionescu, A.M.: ' Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits ', IEEE Int. Solid State Circuit Conf., 2005, p. 260-261, 597
-
(2005)
IEEE Int. Solid State Circuit Conf.
, pp. 260-261
-
-
Ecoffey, S.1
Pott, V.2
Bouvet, D.3
Mazza, M.4
Mahapatra, S.5
Schmid, A.6
Leblebici, Y.7
Declercq, M.J.8
Ionescu, A.M.9
-
7
-
-
0026122410
-
Impact of surrounding gate transistor (SGT) for ultra-high-density LSI
-
0018-9383
-
Takato, H., Sunouchi, K., Okabe, N., Nitayama, A., Hieda, K., Horiguchi, F., and Masuoka, F.: ' Impact of surrounding gate transistor (SGT) for ultra-high-density LSI ', IEEE Trans. Electron. Devices, 1991, 38, (3), p. 573-578 0018-9383
-
(1991)
IEEE Trans. Electron. Devices
, vol.38
, Issue.3
, pp. 573-578
-
-
Takato, H.1
Sunouchi, K.2
Okabe, N.3
Nitayama, A.4
Hieda, K.5
Horiguchi, F.6
Masuoka, F.7
-
8
-
-
0038161696
-
High performance silicon nanowire field effect transistors
-
1530-6984
-
Cui, Y., Zhong, Z., Wang, D., Wang, W.U., and Lieber, C.M.: ' High performance silicon nanowire field effect transistors ', Nano Lett., 2003, 3, (2), p. 149-152 1530-6984
-
(2003)
Nano Lett.
, vol.3
, Issue.2
, pp. 149-152
-
-
Cui, Y.1
Zhong, Z.2
Wang, D.3
Wang, W.U.4
Lieber, C.M.5
-
9
-
-
21044456044
-
Electronic properties of silicon nanowires
-
0018-9383
-
Zheng, Y., Rivas, C., Lake, R., Alam, K., Boykin, T.B., and Klimeck, G.: ' Electronic properties of silicon nanowires ', IEEE Trans. Electron. Devices, 2005, 52, (6), p. 1097-1103 0018-9383
-
(2005)
IEEE Trans. Electron. Devices
, vol.52
, Issue.6
, pp. 1097-1103
-
-
Zheng, Y.1
Rivas, C.2
Lake, R.3
Alam, K.4
Boykin, T.B.5
Klimeck, G.6
-
10
-
-
0842331307
-
A computational study of ballistic silicon nanowire transistors
-
Sect. 29.5
-
Wang, J., Polizzi, E., and Lundstrom, M.: ' A computational study of ballistic silicon nanowire transistors ', IEDM, 2003, p. 695-698, Sect. 29.5
-
(2003)
IEDM
, pp. 695-698
-
-
Wang, J.1
Polizzi, E.2
Lundstrom, M.3
-
11
-
-
0026909715
-
Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)
-
0018-9383
-
Miyano, S., Hirose, M., and Masuoka, F.: ' Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA) ', IEEE Trans. Electron. Devices, 1992, 39, (8), p. 1876-1881 0018-9383
-
(1992)
IEEE Trans. Electron. Devices
, vol.39
, Issue.8
, pp. 1876-1881
-
-
Miyano, S.1
Hirose, M.2
Masuoka, F.3
-
12
-
-
9244243065
-
The design of DNA self-assembled computing circuitry
-
1063-8210
-
Dwyer, C., Vicci, L., Poulton, J., Erie, D., Superfine, R., Washburn, S., and Taylor, R.M.: ' The design of DNA self-assembled computing circuitry ', IEEE Trans. VLSI Syst., 2004, 12, (11), p. 1214-1220 1063-8210
-
(2004)
IEEE Trans. VLSI Syst.
, vol.12
, Issue.11
, pp. 1214-1220
-
-
Dwyer, C.1
Vicci, L.2
Poulton, J.3
Erie, D.4
Superfine, R.5
Washburn, S.6
Taylor, R.M.7
-
13
-
-
3042742837
-
Performance simulation of nanoscale silicon rod field-effect transistor logic
-
1536-125X
-
Dwyer, C., Vicci, L., and Taylor, R.M.: ' Performance simulation of nanoscale silicon rod field-effect transistor logic ', IEEE Trans. Nanotechnol., 2003, 2, (2), p. 69-74 1536-125X
-
(2003)
IEEE Trans. Nanotechnol.
, vol.2
, Issue.2
, pp. 69-74
-
-
Dwyer, C.1
Vicci, L.2
Taylor, R.M.3
-
14
-
-
0019049847
-
Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor
-
0018-9383
-
Ogura, S., Tsang, P.J., Walker, W.W., Critchlow, D.L., and Shepard, J.F.: ' Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor ', IEEE Trans. Electron. Devices, 1980, 27, (8), p. 1359-1367 0018-9383
-
(1980)
IEEE Trans. Electron. Devices
, vol.27
, Issue.8
, pp. 1359-1367
-
-
Ogura, S.1
Tsang, P.J.2
Walker, W.W.3
Critchlow, D.L.4
Shepard, J.F.5
-
15
-
-
0024105667
-
A physically based mobility model for numerical simulation of non-planar devices
-
0278-0070
-
Lombardi, C., Manzini, S., Saporito, A., and Vanzi, M.: ' A physically based mobility model for numerical simulation of non-planar devices ', IEEE Trans. Comput. Aided Des., 1988, 7, (11), p. 1164-1171 0278-0070
-
(1988)
IEEE Trans. Comput. Aided Des.
, vol.7
, Issue.11
, pp. 1164-1171
-
-
Lombardi, C.1
Manzini, S.2
Saporito, A.3
Vanzi, M.4
-
17
-
-
0026837568
-
Simulation of ultra small GaAs MESFET using quantum moment equations
-
0018-9383
-
Zhou, J.R., and Ferry, D.K.: ' Simulation of ultra small GaAs MESFET using quantum moment equations ', IEEE Trans. Electron. Devices, 1992, 39, p. 473-478 0018-9383
-
(1992)
IEEE Trans. Electron. Devices
, vol.39
, pp. 473-478
-
-
Zhou, J.R.1
Ferry, D.K.2
-
18
-
-
0026908536
-
Simulation of ultra small GaAs MESFET using quantum moment equations-II: Velocity overshoot
-
0018-9383
-
Zhou, J.R., and Ferry, D.K.: ' Simulation of ultra small GaAs MESFET using quantum moment equations-II: velocity overshoot ', IEEE Trans. Electron. Devices, 1992, 39, p. 1793-1796 0018-9383
-
(1992)
IEEE Trans. Electron. Devices
, vol.39
, pp. 1793-1796
-
-
Zhou, J.R.1
Ferry, D.K.2
-
19
-
-
0028515347
-
In-plane transport properties of Si/Si(1-x)Ge(x) structure and its FET performance by computer simulation
-
0018-9383
-
Yamada, T., Zhou, J.R., Miyata, H., and Ferry, D.K.: ' In-plane transport properties of Si/Si(1-x)Ge(x) structure and its FET performance by computer simulation ', IEEE Trans. Electron. Devices, 1994, 41, p. 1513-1522 0018-9383
-
(1994)
IEEE Trans. Electron. Devices
, vol.41
, pp. 1513-1522
-
-
Yamada, T.1
Zhou, J.R.2
Miyata, H.3
Ferry, D.K.4
-
20
-
-
0035249575
-
Quantum device-simulation with the density-gradient model on unstructured grids
-
0018-9383
-
Wettstein, A., Schenk, A., and Fichtner, W.: ' Quantum device-simulation with the density-gradient model on unstructured grids ', IEEE Trans. Electron. Devices, 2001, 48, (2), p. 279-283 0018-9383
-
(2001)
IEEE Trans. Electron. Devices
, vol.48
, Issue.2
, pp. 279-283
-
-
Wettstein, A.1
Schenk, A.2
Fichtner, W.3
-
22
-
-
0027667486
-
Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications
-
0040-6090
-
Bindal, A., Rovedo, N., Restivo, J., Galli, C., and Ogura, S.: ' Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications ', Thin Solid Films, 1993, 232, p. 105-109 0040-6090
-
(1993)
Thin Solid Films
, vol.232
, pp. 105-109
-
-
Bindal, A.1
Rovedo, N.2
Restivo, J.3
Galli, C.4
Ogura, S.5
-
23
-
-
23744492075
-
A review of 0.18-μm full adder performances for tree structured arithmetic circuits
-
1063-8210
-
Chang, C.H., Gu, J., and Zhang, M.: ' A review of 0.18-μm full adder performances for tree structured arithmetic circuits ', IEEE Trans. VLSI Syst., 2005, 13, (6), p. 686-695 1063-8210
-
(2005)
IEEE Trans. VLSI Syst.
, vol.13
, Issue.6
, pp. 686-695
-
-
Chang, C.H.1
Gu, J.2
Zhang, M.3
-
24
-
-
0036999969
-
Analysis and comparison on full adder block in submicron technology
-
1063-8210
-
Alioto, M., and Palumbo, G.: ' Analysis and comparison on full adder block in submicron technology ', IEEE Trans. VLSI Syst., 2002, 10, (6), p. 806-823 1063-8210
-
(2002)
IEEE Trans. VLSI Syst.
, vol.10
, Issue.6
, pp. 806-823
-
-
Alioto, M.1
Palumbo, G.2
-
25
-
-
0036476973
-
Performance analysis of low-power 1-Bit CMOS full adder cells
-
1063-8210
-
Shams, A.M., Darwish, T.K., and Bayoumi, M.A.: ' Performance analysis of low-power 1-Bit CMOS full adder cells ', IEEE Trans. VLSI Syst., 2002, 10, (1), p. 20-29 1063-8210
-
(2002)
IEEE Trans. VLSI Syst.
, vol.10
, Issue.1
, pp. 20-29
-
-
Shams, A.M.1
Darwish, T.K.2
Bayoumi, M.A.3
-
26
-
-
0036296689
-
Performance analysis of single-bit full adder cells using 0.18, 0.25 and 0.35m CMOS technologies
-
Sayed, M., and Badawy, W.: ' Performance analysis of single-bit full adder cells using 0.18, 0.25 and 0.35m CMOS technologies ', IEEE Int. Symp. Circuits Sys., 2002, p. 559-562
-
(2002)
IEEE Int. Symp. Circuits Sys.
, pp. 559-562
-
-
Sayed, M.1
Badawy, W.2
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