SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

IEEE Transactions on Nanotechnology

Volumn 4, Issue 2, 2005, Pages 242-246

  Park, Kyu Sul ^a   Kim, Sang Jin ^b   Back, In Bok ^b,c   Lee, Won Hee ^d   Kang, Jong Seuk ^e   Jo, Yong Bum ^b   Lee, Sang Don ^b   Lee, Chang Keun ^b   Choi, Jung Bum ^b,f   Kim, Jang Han ^b   Park, Keun Hyung ^b   Cho, Won Ju ^c   Jang, Moon Gyu ^c   Lee, Seong Jae ^c  

^a SAMSUNG Electronics   (South Korea)

^b Chungbuk National University   (South Korea)

^c Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^d Hynix Semiconductor Inc   (South Korea)

^e LG Display Co Ltd   (South Korea)

^f National Program for Tera Level Devices   (South Korea)

Author keywords

Pattern dependent oxidation (PADOX); Peak to valley current ratio (PVCR); SET logic cells; Silicon on insulator; Single electron transistor; Single electron transistor (SET) field effect transistor (FET) hybrid integrated circuits (ICs)

Indexed keywords

COULOMB BLOCKADE; ELECTRIC CONDUCTANCE; ELECTRIC POTENTIAL; ELECTRON BEAM LITHOGRAPHY; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; LOGIC DEVICES; OXIDATION;

PATTERN DEPENDENT OXIDATION (PADOX); PEAK-TO-VALLEY CURRENT RATIO (PVCR); SET-LOGIC CELLS; SINGLE ELECTRON TRANSISTORS; SINGLE ELECTRON TRANSISTORS (SET); TERAHERTZ INTRINSIC SPEEDS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 15844381591     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.837857     Document Type: Article

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