A rigorous study of measurement techniques for negative bias temperature instability

IEEE Transactions on Device and Materials Reliability

Volumn 8, Issue 3, 2008, Pages 526-535

  Grasser, Tibor ^a   Wagner, Paul Jürgen ^a   Hehenberger, Philipp ^a   Goes, Wolfgang ^a   Kaczer, Ben ^b  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b IMEC   (Belgium)

Author keywords

Interface states; Measure stress measure (MSM); Measurement; Negative bias temperature instability (NBTI); On the fly (OTF); Oxide charges

Indexed keywords

DEGRADATION; DRAIN CURRENT; MOSFET DEVICES; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

INTERFACE STATES; MEASURE/STRESS/MEASURE (MSM); NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); ON-THE-FLY (OTF); OXIDE CHARGES;

NEGATIVE TEMPERATURE COEFFICIENT;

EID: 54949098896     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2002353     Document Type: Article

References (32)

1. A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI impact on transistor and circuit: Models, mechanisms and scaling effects [MOSFETs]," in IEDM Tech. Dig., 2003, pp. 14.5.1-14.5.4.
2. V. Huard, M. Denais, and C. Parthasarathy, "NBTI degradation: From physical mechanisms to modelling," Microelectron. Reliab., vol. 46, no. 1, pp. 1-23, Jan. 2006.
3. S. Mahapatra, K. Ahmed, D. Varghese, A. E. Islam, G. Gupta, L. Madhav, D. Saha, and M. A. Alam, "On the physical mechanism of NBTI in silicon oxynitride p-MOSFETs: Can differences in insulator processing conditions resolve the interface trap generation versus hole trapping controversy?" in Proc. IRPS, 2007, pp. 1-9.
4. B. Kaczer, V. Arkhipov, R. Degraeve, N. Collaert, G. Groeseneken, and M. Goodwin, "Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification," in Proc. IRPS, 2005, pp. 381-387.
5. th-measurements," in Proc. IRPS, 2006, pp. 448-453.
6. G characteristics," IEEE Electron Device Lett., vol. 27, no. 1, pp. 55-57, Jan. 2006.
7. D. Heh, R. Choi, C. D. Young, B. H. Lee, and G. Bersuker, "A novel bias temperature instability characterization methodology for high-k nMOSFETs," IEEE Electron Device Lett., vol. 27, no. 10, pp. 849-851, Oct. 2006.
8. T. Grasser and B. Kaczer, "Negative bias temperature instability: Recoverable versus permanent degradation," in Proc. ESSDERC, 2007, pp. 127-130.
9. T. Grasser, B. Kaczer, P. Hehenberger, W. Gos, R. O'Connor, H. Reisinger, W. Gustin, and C. Schlunder, "Simultaneous extraction of recoverable and permanent components contributing to bias-temperature instability," in IEDM Tech. Dig., 2007, pp. 801-804.
10. M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. Rey-Tauriac, and N. Revil, "On-the-fly characterization of NBTI in ultra-thin gate oxide pMOSFETs," in IEDM Tech. Dig., 2004, pp. 109-112.
11. J. F. Zhang and M. H. Chang, "An assessment of effective mobility variation during negative bias temperature instability," ECS Trans., vol. 6, no. 3, pp. 301-311, 2007.
12. H. Reisinger, U. Brunner, W. Heinrigs, W. Gustin, and C. Schlunder, "A comparison of fast methods for measuring NBTI degradation," IEEE Trans. Device Mater. Rel., vol. 7, no. 4, pp. 531-539, Dec. 2007.
13. 2 gate stacks," in IEDM Tech. Dig, 2006, pp. 1-4.
14. M. A. Alam, "A review of characterization methodologies of gate dielectric breakdown and negative bias temperature instability," in Proc. IPFA, Jul. 2006, pp. 25-32.
15. Y. Tsividis, Operation and Modeling of the MOS Transistor. NewYork: McGraw-Hill, 1999.
16. T and β mismatch shifts in pMOSFETs," IEEE Trans. Device Mater. Rel., vol. 2, no. 4, pp. 89-93, Dec. 2002.
17. 2 structures: The influence of surface potential on passivation during post metallization anneal," J. Appl. Phys., vol. 88, no. 2, pp. 938-942, Jul. 2000.
18. T. Grasser, R. Entner, O. Triebl, H. Enichlmair, and R. Minixhofer, "TCAD modeling of negative bias temperature instability," in Proc. SISPAD, Monterey, CA, Sep. 2006, pp. 330-333.
19. J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, "Mismatch characterization of submicron MOS transistors," Analog Integr. Circuits Signal Process., vol. 12, no. 2, pp. 95-106, Feb. 1997.
20. T. Grasser, W. Goes, V. Sverdlov, and B. Kaczer, "The universality of NBTI relaxation and its implications for modeling and characterization," in Proc. IRPS, 2007, pp. 268-280.
21. M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, C. Guerin, G. Ribes, F. Perrier, M. Mairy, and D. Roy, "Paradigm shift for NBTI characterization in ultra-scaled CMOS technologies," in Proc. IRPS, 2006, pp. 735-736.
22. MINIMOS-NT 2.1 User's Guide, Institut fur Mikroelektronik, Technische Universität Wien, Wien, Austria, 2004. IμE. [Online]. Available: www.iue.tuwien.ac.at
23. C. Jungemann, T. Grasser, B. Neinhüs, and B. Meinerzhagen, "Failure of moments-based transport models in nanoscale devices near equilibrium," IEEE Trans. Electron Devices, vol. 52, no. 11, pp. 2404-2408, Nov. 2005.
24. J. P. Campbell, P. M. Lenahan, A. T. Krishnan, and S. Krishnan, "Density of states and structure of NBTI-induced defects in plasma-nitrided pMOSFETs," in Proc. IRPS, 2007, pp. 503-510.
25. V. M. Agostinelli, Jr., H. Shin, and A. F. Tasch, Jr., "A comprehensive model for inversion layer hole mobility for simulation of submicrometer MOSFETs," IEEE Trans. Electron Devices, vol. 38, no. 1, pp. 151-159, Jan. 1991.
26. A. Haggag, G. Anderson, S. Parihar, D. Burnett, G. Abeln, J. Higman, and M. Moosa, "Understanding SRAM high-temperature-operating-life NBTI: Statistics and permanent vs recoverable damage," in Proc. IRPS, 2007, pp. 452-456.
27. A. E. Islam, E. N. Kumar, H. Das, S. Purawat, V. Maheta, H. Aono, E. Murakami, S.Mahapatra, andM. A. Alam, "Theory and practice of on-the-fly and ultra-fast VT measurements for NBTI degradation: Challenges and opportunities," in IEDM Tech. Dig., 2007, pp. 805-808.
28. A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, "Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2143-2154, Sep. 2007.
29. D. Bauza, "Rigorous analysis of two-level charge pumping: Application to the extraction of interface trap concentration versus energy profiles in metal-oxide-semiconductor transistors," J. Appl. Phys., vol. 94, no. 5, pp. 3239-3248, Sep. 2003.
30. D. Goguenheim, D. Vuillaume, G. Vincent, and N.M. Johnson, "Accurate measurements of capture cross sections of semiconductor insulator interface states by a trap-filling experiment: The charge-potential feedback effect," J. Appl. Phys., vol. 68, no. 3, pp. 1104-1113, Aug. 1990.
31. T. L. Tewksbury and H.-S. Lee, "Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 239-252, Mar. 1994.
32. C. Shen, M.-F. Li, C. E. Foo, T. Yang, D. M. Huang, A. Yap, G. S. Samudra, and Y.-C. Yeo, "Characterization and physical origin of fast Vth transient in NBTI of pMOSFETs with SiON dielectric," in IEDM Tech. Dig., 2006, pp. 1-4.