The statistics of NBTI-induced V T and β mismatch shifts in pMOSFETs

IEEE Transactions on Device and Materials Reliability

Volumn 2, Issue 4, 2002, Pages 89-93

  Rauch III, Stewart E ^a,b  

^a IEEE   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

FET analog integrated circuits; MOS transistor mismatch; Negative bias temperature instability (NBTI); Reliability; Statistics

Indexed keywords

DRAIN CURRENTS; MOS TRANSISTOR MISMATCH; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI);

ELECTRIC CURRENTS; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; RELIABILITY THEORY; STATISTICAL METHODS;

MOSFET DEVICES;

EID: 0041358085     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2002.805119     Document Type: Article

References (13)

1. C. E. Blat, E. H. Nicollian, and E. H. Poindexter, "Mechanism of negative-bias-temperature instability," J. Appl. Phys., vol. 69, no. 3, pp. 1712-1720, 1991.
2. 2 (4-6 nm)-Si interfaces during negative-bias temperature aging," J. Appl. Phys., vol. 77, no. 3, pp. 1137-1148, 1995.
3. N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, and T. Horiuchil, "NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation," in Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, June 2000, pp. 92-93.
4. P. Chaparala, J. Shibley, and P. Lim, "Threshold voltage drift in pMOSFETS due to NBTI and HCI," in IEEE Int. Integrated Reliability Workshop Final Report, Lake Tahoe, CA, Oct. 2000, pp. 95-97.
5. A. Acovic, E. Crabbé, F. Guarin, G. La Rosa, J. Lukaitis, and S. Rauch, "NBTI-channel hot carrier effects in pMOSFETs in advanced CMOS technologies," in Proc. IEEE Int. Reliability Physics Symp., Denver, CO, Apr. 1997, pp. 282-286.
6. R. Thewes, R. Brederlow, C. Schündler, P. Wieczorek, A. Hesener, B. Ankele, P. Klein, S. Kessel, and W. Weber, "Device reliability in analog CMOS applications," IEEE Trans. Electron Devices, vol. 45, pp. 2505-2513, Dec. 1998.
7. B. Agarwala, M. Armacost, S. Biesemans, L. Burrell, B. Chen, K. Han, D. Harmon, J. Heidenreich, K. Holloway, T. Hook, S. Kapur, T. Kebede, D. Riesling, P. Kim, G. Matusiewicz, J. Lukaitis, P. Nguyen, N. Prabhakara, S. Rauch, N. Rovedo, L. Saraf, J. Slinkman, H. Tang, R. Wong, S. Yankee, K. Allers, A. Augustin, G. Brase, E. Demm, C. Derby, G. Friese, F. Grellner, E. Kaltalioglu, M. Hoinkis, C. Lin, R. Mahnkopf, O. Prigge, T. Schafbauer, T. Schiml, K. Schruefer, S. Srinivasan, M. Stetter, G. Unger, and R. Zoeller, "A 0.18-μm dual gate (3.5 nm/6.8 nm) CMOS technology with copper metallurgy for logic, SRAM, and analog applications," in Proc. 29th Eur. Solid State Device Research Conf., Leuven, Belgium, Sept. 1999, pp. 632-635.
8. T. Schiml, S. Biesemans, G. Brase, L. Burrell, A. Cowley, K. C. Chen, A. Von Ehrenwall, B. Von Ehrenwall, P. Felsner, J. Gill, F. Grellner, F. Guarin, L. K. Han, M. Hoinkis, E. Hsiung, E. Kaltalioglu, P. Kim, G. Knoblinger, S. Kulkarni, A. Leslie, T. Mono, T. Schafbauer, U. Schroeder, K. Schniefer, T. Spooner, D. Warner, C. Wang, R. Wong, E. Demm, and P. Leung, "A 0.13-μm CMOS platform with Cu/Low-k interconnects for system on chip applications," in Symp. VLSI Technology Dig. Tech. Papers, Kyoto, Japan, June 2001, pp. 101-102.
9. +-polysilicon gatedultrathin oxides (21-26 Å)," in Symp. VLSI Technology Dig. Tech. Papers, Kyoto, Japan, June 1997, pp. 149-150.
10. T.-H. Yeh, J. C. H. Lin, S.-C. Wong, H. Huang, and J. Y. C. Sun, "Mismatch characterization of 1.8-V and 3.3-V devices in 0.18-μm mixed-signal CMOS technology," in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 14, Kobe, Japan, Mar. 2001, pp. 77-82.
11. J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, "Mismatch characterization of submicron MOS transistors," Analog Integrat. Circuits Signal Process., vol. 12, pp. 95-106, 1997.
12. K. Takeuchi, "Channel size dependence of dopant-induced threshold voltage fluctuations," in Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, June 1998, pp. 72-73.
13. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, pp. 2505-2513, Dec. 1998.