A novel bias temperature instability characterization methodology for high-κ nMOSFETs

IEEE Electron Device Letters

Volumn 27, Issue 10, 2006, Pages 849-851

  Heh, Dawei ^a   Choi, Rino ^a   Young, Chadwin D ^a   Lee, Byoung Hun ^a   Bersuker, Gernnadi ^a  

^a SEMATECH   (United States)

Author keywords

Lifetime prediction; Relaxation; Single pulse; Transient charge

Indexed keywords

ANALYSIS METHODS; BIAS-TEMPERATURE INSTABILITIES; FAST TRANSIENTS; LIFETIME PREDICTION; N-MOSFETS; POWER-LAW DEPENDENCES; POWER-LAW EXPONENTS; RELAXATION; SINGLE PULSE; STRESS TIME; THRESHOLD VOLTAGE SHIFTS; TRANSIENT CHARGE;

ELECTRIC BREAKDOWN;

THRESHOLD VOLTAGE;

EID: 49549118892     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.882525     Document Type: Article

References (10)

1. R. Choi, S. J. Rhee, J. C. Lee, B. H. Lee, and G. Bersuer, "Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress," IEEE Electron Device Lett., vol. 26, no. 3, pp. 197-199, Mar. 2005.
2. G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. M. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Niurto, "Effect of pre-existing defects on reliability assessment of high-κ gate dielectrics," Microelectron. Reliab., vol. 44, no. 9-11, pp. 1509-1512, Sep.-Nov. 2004.
3. B. H. Lee, R. Choi, J. Sim, S. Krishnan, J. Peterson, G. A. Brown, and G. Bersuker, "Validity of constant voltage stress based reliability assessment of high-κ devices," IEEE Trans. Device Mater Rel., vol. 5, no. 1, pp. 20-25, Mar. 2005.
4. R. Choi, S. C. Sorg, C. D. Young, G. Bersuker, and B. H. Lee, "Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique," Appl. Rhys. Lett., vol. 87, no. 12, pp. 122901-122903, Sep. 2005.
5. M. Dennis, C. Parthasarathy, G. Ribes Y. Rey-Tauriae, N. Revil, A. Bravaix, V. Huard, and F. Perrier, "On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's," in IEDM Tech. Dig., 2004, pp.109-112.
6. g," IEEE Eletron Device Lett., vol. 26, no. 8, pp. 586-589, Aug. 2005.
7. 2 gate, dielectries," in Proc. Int. Reliab. Phys. Symp., 2003, pp. 41-45.
8. 2 gate dielectrics and frequency dependence of dynamic BTI in MOSFETs," in IEDM Tech. Dig., 2004, pp. 733-736.
9. J. Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman, P. Majhi, J. J. Peterson, S. Gopalan, B. Foran, H.-J. Li, B. H. Lee, G. Bersuker, P. Zeitzoff, G. A. Brown, P. Lysaght, C. D. Young, R. W. Murto, and H. R. Huff, "Experimental stndy of etched back thermal oxide, for optimization of the Si/high-κ interface," presented dt the Material Research Society Spring Meeting, San Francisco, CA, 2004, E1.4.1.
10. 2 NMOS transistors," in Proc. Int. Reliab. Phys. Symp., 2006, pp. 179-183.