45 nm/32 nm CMOS - Challenge and perspective

Solid-State Electronics

Volumn 52, Issue 9, 2008, Pages 1266-1273

  Ishimaru, Kazunari ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; METALS; TECHNOLOGICAL FORECASTING; TECHNOLOGY;

45NM NODE; 65-NM NODES; ARF IMMERSION LITHOGRAPHY; BARRIER LAYER; HIGH-K GATE INSULATOR; METAL GATES; NEW TECHNOLOGY DEVELOPMENT; NODE TECHNOLOGY;

NANOTECHNOLOGY;

COMPETITION; INSULATORS; LITHOGRAPHY; SEMICONDUCTOR DEVICES;

EID: 50349099157     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.04.034     Document Type: Article

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