A low leakage SRAM macro with replica cell biasing scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 166-167

  Takeyama, Y ^a   Otake, H ^a   Hirabayashi, O ^a   Kushida, K ^a   Otsuka, N ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33745118352     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469357     Document Type: Conference Paper

References (2)

1. M. Yamaoka, et al., ISSCC Tech. Dig., pp. 494-495, Feb. 2004.
2. K. Nii, et al., Symp. VLSI Cir. Dig., pp. 247-250, Jun. 2003.