High performance CMOSFET technology for 45nm generation

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 166-167

  Oishi, A ^a   Komoda, T ^a   Morimasa, Y ^a   Sanuki, T ^a   Yamasaki, H ^a   Hamaguchi, M ^a   Oouchi, K ^a   Matsuo, K ^a   Iinuma, T ^a   Itoh, T ^a   Takegawa, Y ^a   Iwai, M ^a   Sunouchi, K ^a   Noguchi, T ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; CRYSTALLIZATION; ION IMPLANTATION; NANOTECHNOLOGY; PHOSPHORUS; SEMICONDUCTOR JUNCTIONS;

65NM TECHNOLOGY; ACTIVATION PROCESS; CMOSFET TECHNOLOGY; SOURCE & DRAIN EXTENSION (SDE);

MOSFET DEVICES;

EID: 4544361502     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345458     Document Type: Conference Paper

References (6)

1. A.Oishi et al., IEDM Tech. Dig., pp.507, 2001.
2. T. Ito et al., Symp. VLSI Tech. Dig., pp53, 2003
3. A. Shima et al., IEDM Tech. Dig., pp.493, 2003
4. T.Yamainoto et al., Symp. VLSI Tech. Dig., pp138, 2002
5. H. Park et al., IEDM Tech. Dig., pp.635, 2003
6. van Meer, H et al., Symp. VLSI Tech. Dig., pp170, 2002