A highly dense, high-performance 130nm node CMOS technology for large scale system-on-a-chip applications

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 575-578

  Ootsuka, F ^a   Wakahara, S ^a   Ichinose, K ^a   Honzawa, A ^a   Wada, S ^a   Sato, H ^a   Ando, T ^a   Ohta, H ^a   Watanabe, K ^a   Onai, T ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT SEMICONDUCTOR DEVICES; LEAKAGE CURRENTS; SILICON NITRIDE; STATIC RANDOM ACCESS STORAGE; STRESS ANALYSIS; TENSILE STRENGTH;

SYSTEM-ON-A-CHIP (SOC);

CMOS INTEGRATED CIRCUITS;

EID: 17344377630     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. NMOS drive current reduction caused by transistor layout and trench isolation induced stress
2. 100nm gate length high performance/low power CMOS transistor structure
3. 0.1-μm CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate system
4. A 1.2V, sub-0.09mm gate length CMOS technology
5. A modular 0.13μm bulk CMOS technology for high performance and low power applications