High performance ultra low-k (k=2.0/keff=2.4)/Cu dual-damascene interconnect technology with self-formed MnSixOy barrier layer for 32 nm-node

2006 International Interconnect Technology Conference, IITC

Volumn , Issue , 2006, Pages 216-218

  Usui, T ^a   Tsumura, K ^a   Nasu, H ^a   Hayashi, Y ^a   Minamihaba, G ^a   Toyoda, H ^a   Sawada, H ^a   Ito, S ^a   Miyajima, H ^a   Watanabe, K ^a   Shimada, M ^a   Kojima, A ^a   Uozumi, Y ^a   Shibata, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; MANGANESE COMPOUNDS; METALS; SILICON CARBIDE; TECHNOLOGY;

COPPER (CU); DUAL-DAMASCENE; EFFECTIVE DIELECTRIC CONSTANTS; HARD MASKS; INTER-LEVEL DIELECTRIC; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; METAL LAYERS; METALLIZATION; PLASMA-INDUCED DAMAGE; PROTECTION LAYERS; SPIN-ON; STRESS-INDUCED VOIDING; ULTRA LOW-K; VIA RESISTANCE;

DIELECTRIC MATERIALS;

EID: 50249085516     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2006.1648692     Document Type: Conference Paper

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