High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 229-232

  Oishi, A ^a   Fujii, O ^a   Yokoyama, T ^a   Ota, K ^b   Sanuki, T ^a   Inokuma, H ^a   Eda, K ^a   Idaka, T ^a   Miyajima, H ^a   Iwasa, S ^a   Yamasaki, H ^a   Oouchi, K ^a   Matsuo, K ^a   Nagano, H ^a   Komoda, T ^a   Okayama, Y ^a   Matsumoto, T ^b   Fukasaku, K ^b   Shimizu, T ^a   Miyano, K ^a   Suzuki, T ^a   Yahashi, K ^a   Horiuchi, A ^b   Takegawa, Y ^a   Saki, K ^a   Mori, S ^a   Ohno, K ^b   Mizushima, I ^a   Saito, M ^b   Iwai, M ^a   Yamada, S ^a   Nagashima, N ^b   Matsuoka, F ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON MOBILITY; SCALABILITY; SEMICONDUCTOR JUNCTIONS; SILICON NITRIDE; STRESSES;

GATE STACK SCALING; PROCESS INDUCED MOBILITY; SHORT CHANNEL EFFECT (SCE); STRESS ENHANCEMENT FACTORS;

MOSFET DEVICES;

EID: 33846276277     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iedm.2005.1609314     Document Type: Conference Paper

References (7)

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