Performance of immersion lithography for 45nm-node CMOS and ultra-high density SRAM with 0.25um2

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6520, Issue PART 1, 2007, Pages

  Mimotogi, Shoji ^a   Uesawa, Fumikatsu ^b   Tominaga, Makoto ^c   Fujise, Hiroharu ^a   Sho, Koutaro ^a   Katsumata, Mikio ^b   Hane, Hiroki ^b   Ikegami, Atsushi ^b   Nagahara, Seiji ^c   Ema, Tatsuhiko ^a   Asano, Masafumi ^a   Kanai, Hideki ^a   Kimura, Taiki ^a   Iwai, Masaaki ^a  

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

45nm CMOS; Alt.PSM; Att.PSM; Immersion lithography; Lithography design; Ultra high density SRAM

Indexed keywords

LITHOGRAPHY; PHASE SHIFT; STATIC RANDOM ACCESS STORAGE;

GATE LEVELS; IMMERSION LITHOGRAPHY; LITHOGRAPHY DESIGN; ULTRA HIGH DENSITY SRAM;

CMOS INTEGRATED CIRCUITS;

EID: 35148890831     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.711049     Document Type: Conference Paper

References (4)

1. F. Uesawa et al., "Lithography of choice for the 45-nm node: new medium, new wavelength, or new beam?", SPIE Vol. 5377, 34(2004)
2. S.Mimotogi et al., "Optical Lithography Technologies for 45nm-Node CMOS", SPIE Vol.5754, 196(2005)
3. Kohji Hashimoto et al., "ArF Lithography Technologies for 65nm-node CMOS (CMOS5) with 30nm Logic Gate and High Density Embedded Memories", Proc. of VLSI symposium 2003, 4B-2
4. B.J.Lin, "The k3 coefficient in nonparaxial scaling equation for resolution, depth of focus, and immersion lithography, JM3-Journal of Microlithography, Microfabrication, and Microsystems 2002,1(1):7-12.