Fast DNBTI components in p-MOSFET with SiON dielectric

IEEE Electron Device Letters

Volumn 26, Issue 11, 2005, Pages 826-828

  Yang, T ^a,b   Shen, C ^a,b   Li, M F ^a,b   Ang, C H ^c   Zhu, C X ^b   Yeo, Y C ^b   Samudra, G ^b   Rustagi, Subhash C ^a   Yu, M B ^a   Kwong, D L ^d  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c Chartered Semiconductor Manufacturing   (Singapore)

^d The University of Texas at Austin   (United States)

Author keywords

Dynamic negative biased temperature instability (DNBTI); MOSFETs; SiON

Indexed keywords

COMPUTER SIMULATION; DEGRADATION; DIELECTRIC DEVICES; ELECTRON TRAPS; GATES (TRANSISTOR); HOLE TRAPS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MODELS; STRESSES; THERMODYNAMIC STABILITY; ULTRATHIN FILMS;

CUMULATIVE DEGRADATION; DETRAPPING; DYNAMIC NEGATIVE BIASED TEMPERATURE INSTABILITY (DNBTI); GATE DIELECTRIC; STRESS FREQUENCY;

MOSFET DEVICES;

EID: 27744444546     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.857684     Document Type: Article

References (12)

1. G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D.-L. Kwong, "Dynamic NBTI for p-MOS transistors and its impact on MOSFET scaling," IEEE Electron Device Lett., vol. 23, no. 11, pp. 734-736, Nov. 2002.
2. G. Chen, K. Y. Chuah, M. F. Li, D. S. H. Chan, C. H. Ang, J. Z. Zheng, Y. Jin, and D.-L. Kwong, "Dynamic NBTI of pMOS transistor and its impact on device lifetime," in Proc. lEEE Reliab. Phys. Symp., 2003, pp. 196-202.
3. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for PMOSFETs," in IEDM Tech. Dig., 2003, pp. 345-348.
4. S. Mahapatra, M. A. Alam, P. B. Kumar, T. R. Dalei, and D. Saha, "Mechanism of negative bias temperature instability in CMOS devices: Degradation, recovery and impact of nitrogen," in IEDM Tech. Dig., 2004, pp. 105-108.
5. S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," in Proc. IEEE Reliab. Phys. Symp., 2004, pp. 273-282.
6. V. Huard and M. Denais, "Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS," in Proc. IEEE Reliab. Phys. Symp., 2004, pp. 40-45.
7. W. Abadeer and W. Ellis, "Behavior of NBTI under AC dynamic circuit conditions," in Proc. IEEE Reliab. Phys. Symp., 2003, pp. 17-22.
8. E. Ershov, S. Saxena, H. Karbasi, S. Winters, S. Minehane, J. Babcock, R. Lindley, P. Clifton, M. Redford, and A. Shibkov, "Dynamic recovery of negative bias temperature instability in p-type metal-oxidesemiconductor field-effect-transistors," Appl. Phys. Lett., vol. 83, pp. 1647-1649, 2003.
9. 2 gate dielectrics and frequency dependence of dynamic BTI in MOSFETs," in IEDM Tech. Dig., 2004, pp. 733-736.
10. 2 gate dielectrics," in Proc. IEEE Reliab. Phys. Symp., 2003, pp. 41-45.
11. 2," J. Appl. Phys., vol. 58, pp. 2252-2261, 1985.
12. S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, "Charge trapping in high-κ gate dielectric stacks," in IEDM Tech. Dig., 2002, pp. 517-520.