Case study of reliability-aware and low-power design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 7, 2008, Pages 861-873

  Yang, Shengqi ^a,b,c   Wang, Wenping ^a,d   Lu, Tiehan ^a,b,c   Wolf, Wayne ^a,c,e   Vijaykrishnan, N ^a,f   Xie, Yuan ^a,f  

^a IEEE

^b Princeton University   (United States)

^c INTEL CORPORATION   (United States)

^d Arizona State University   (United States)

^e GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^f The Pennsylvania State University   (United States)

Author keywords

Circuit reliability; Dynamic voltage scaling (DVS); Low power; SRAM; Systems on a chip (SOC); Voltage island partitioning and floorplanning

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

ALGORITHM DESIGNS; BALANCE RELIABILITY; CASE STUDIES; DESIGN METHODOLOGIES; DYNAMIC VOLTAGE SCALING (DVS); FLOOR-PLANNING; LOW POWERS; LOW-POWER DESIGNS; NEW DESIGN; POWER REDUCTIONS; RELIABILITY CHARACTERIZATION; SRAM CELLS; SYSTEM-ON-A-CHIP (SOC) DESIGNS; VOLTAGE ISLANDS;

VOLTAGE STABILIZING CIRCUITS;

EID: 48149095669     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000460     Document Type: Article

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